MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 137

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
11.2
Since the MT92210 interfaces with a TDM bus, it is necessary that it incorporate a clock recovery circuit that will
allow it to generate a precise TDM clock. As such, the MT92210 contains data gathering hardware to accumulate
information concerning timing VCs or channels, as well as clock generation mechanisms.
The first portion of the clock recovery is a point gathering system that feeds software with all the information it
needs to obtain a very precise measurement of the clock it needs to generate. The module receives pulses
obtained either from the UTOPIA module (timing reference VCs) or from the RTP RX SAR (timing reference
packets). These pulses can then be filtered, so that only a single pulse out of N is actually kept and treated by the
hardware: this artificially “slows down” the timing reference signal by a factor of N.
In parallel, free running counters of mem_clk and of the adap_ref signal are kept, giving a very good idea of the
time at which each pulse is received. When a pulse is kept by the filtering algorithm, a clock recovery event
structure is written to external memory, with the 32-bit mem_clk counter, the 32-bit adap_ref counter and a 16-bit
fraction of the adap_ref counter, as well as the LI and UUI of the received mini-packet. These event structures are
written to a buffer in external memory, and the clock recovery module will generate an interrupt when the buffer is
more than half full. Because clock recovery events arrive at a fixed rate, the size of the buffer chosen will
completely determine the rate at which it needs to be serviced.
Clock Recovery
The Adaptive Clock Recovery Event Queue is a circular buffer in SSRAM A used to report
packet reception events to the host processor. It can be programmed to sizes of 4K bytes to
128K bytes in steps of 2^k. It must be mapped on a base address of its size. The position and
size of this queue can be programmed at register address 0xB20 and 0xB28, for queue A
and B respectively.
+A
+C
+E
+0
+2
+4
+6
+8
b15
Figure 80 - Adaptive Clock Recovery RTP Event Structure
b14
Figure 79 - Adaptive Clock Recovery Event Queue
mem_clk_sar_i Cycles Since Last Reference Clock Rise [15:0]
b13
+(N-2)*10h
+(N-1)*10h
b12
+10
+0
b11
Reference Clock Counter [31:16]
Reference Clock Counter [15:0]
mem_clk_sar_i Counter [31:16]
RTP Sequence Number [15:0]
mem_clk_sar_i Counter [15:0]
b10
Zarlink Semiconductor Inc.
RTP Timestamp [31:16]
R TP Ti m est am p [ 15: 0]
b9
b8
E vent N-2
E vent N-1
E vent 0
E vent 1
b7
b6
b5
b4
b3
b2
b1
b0
MT92210
137