MT93L04A Zarlink Semiconductor, MT93L04A Datasheet - Page 32

• Manufacturer Part Number: MT93L04A
• Manufacturer: Zarlink Semiconductor

MT93L04A
Test Data Registers
As specified in IEEE 1149.1, the MT93L00 JTAG Interface contains three test data registers:
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•
•
Register Descriptions
32
Reset
Reset
Bit
Boundary-Scan register
Bypass Register
Device Identification register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around
the boundary of the MT93L00 core logic.
The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO.
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
7
6
5
4
3
2
1
7
7
Echo Canceller A, Control Register A1
Echo Canceller B, Control Register B1
INJDis
INJDis
6
6
Bypass
AdpDis
INJDis
Name
Reset
0 or 1
BBM
PAD
BBM
BBM
5
5
PAD
PAD
4
4
When high, the power-up initialization is executed which presets all register bits
including this bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low noise injection is
enabled.
When high the Back to Back configuration is enabled.
When low the Normal configuration is enabled.
Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register A1 and
Control Register B1) of the same group to the same logic value to avoid conflict.
When high, 12dB of attenuation is inserted into the Rin to Rout path.
When low the Rin to Rout path gain is 0dB.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped.
When low, output data on both Sout and Rout is a function of the echo canceller
algorithm.
When high, echo canceller adaptation is disabled. The MT93L00 cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Bypass
Bypass
3
3
AdpDis
AdpDis
2
2
1
1
0
1
ExtDl
0
0
0
Read/Write Address: 00
Reset Value:
Read/Write Address: 20
Reset Value:
Description
Preliminary Information
00
02
H
H
H
H
.
.
+ Base Address
+ Base Address