MT93L04AG Zarlink Semiconductor, MT93L04AG Datasheet - Page 36

• Manufacturer Part Number: MT93L04AG
• Description: Description = 128-Channel Voice Echo CANceller ;; Package Type = Bga ;; No. Of Pins = 365
• Manufacturer: Zarlink Semiconductor

MT93L04A
SSC
decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter,
where SS = 4 x2
filter. The default value of SSC
to be used for the decay of MU where each step has a period of SS taps (see SSC
exponential decay is defined as:
Filter Length (512 or 1024) - [Decay Step Number (NS
For example, if NS
x (4x2
36
7-4
6-4
3-0
Bit
Bit
3
2
1
0
7
res
2-0
0
7
7
Echo Canceller A, Control Register A3
Echo Canceller B, Control Register B3
Echo Canceller A, Control Register A4
Echo Canceller B, Control Register B4
4
)] = 256 taps for a filter length of 512 taps.
Decay Step Size Control
SD
res
6
6
2
PathDet
SupDec
RingClr
PathClr
Name
Name
res
res
res
SSC
SD
0
res
5
5
1
7-0
2-0
=4 and SSC
. For example; If SSC
SD
res
4
4
0
Reserved bits. Must always be set to zero for normal operation.
When high, the instability detector is activated. When low, the instability detector is
disabled
When high, the current echo channel estimate will be cleared and the echo canceller
will enter fast convergence mode upon detection of a path change. When low, the
echo canceller will keep the current path estimate but revert to fast convergence
mode upon detection of a path change. Note: this bit is ignored if PathDet is low.
When high, the path change detector is activated. When low, the path change
detector is disabled.
Reserved bit. Must always be set to zero for normal operation.
Must be set to zero.
These three bits control how long the echo canceller remains in a fast convergence
state following a path change, Reset or Bypass operation. A value of zero will keep
the echo canceller in fast convergence indefinitely.
Reserved bits. Must always be set to zero for normal operation.
RingClr
res
3
3
2-0
:
This register controls the step size (SS) to be used during the exponential
2-0
PathClr
is 04h.NS
res
2
2
=4, then the exponential decay start value is 512 - [NS
PathDet
res
1
1
2-0
7-0
= 4, then MU is reduced by a factor of 2 every 64 taps of the FIR
Decay Step Number: This register defines the number of steps
res
res
0
0
7-0
) x Step Size (SS)] where SS = 4 x2
Read/Write Address: 08
Read/Write Address: 28
Reset Value:
Read/Write Address: 09
Read/Write Address: 29
Reset Value:
Description
Description
Preliminary Information
0A
50
H
H
H
H
H
H
.
+ Base Address
+ Base Address
+ Base Address
+ Base Address
.
2-0
7-0
). The start of the
SSC
x SS] = 512 - [4
2-0
.