MT933CG Zarlink Semiconductor, MT933CG Datasheet - Page 4

• Manufacturer Part Number: MT933CG
• Description: 3.3V 10/100 Fast Ethernet Transceiver to MII
• Manufacturer: Zarlink Semiconductor

The Manchester data stream will be decoded into a 4-
bit parallel data bus, RXD[3:0]. The RXD bus is
clocked out on RX_CLK rising. The MT933 must
detect the first 4 bits of pre-amble before RX_DV is
set high.
coding violation will set RX_ER high. RX_DV is reset
by a continuous sequence of zeroes, or by the end-
of-packet IDLE terminator (11 11 00 00). Whilst RX_DV
is low, the data is invalid.
100MHz Synthesizer
This synthesizer employs a delay-locked loop (DLL)
to generate a 100MHz timing reference from the
25MHz reference clock. This 100MHz reference is
used by the 10BASE-T transmit and receive functions
and is divided by 5 to provide a 20MHz data strobe.
The 20MHz clock is used to derive the 2.5 MHz
TX_CLK in 10BASE-T mode.
disabled when not in 10BASE-T mode.
TX10 Pulse Shaper & Filter
The Pulse Shaper & Filter employs a digital Finite
Impulse Response filter (FIR) to pre-compensate for
line distortion and to remove high frequency
components in accordance with the 802.3 Standard.
The Pulse Shaper & Filter is disabled when not in
10BASE-T mode.
TX10 Latency
When connected to appropriate magnetics the latency
through the TX10 path is less than 2BT (200ns) for
data transmissions. This timing is measured from the
rising edge of TX_CLK to the output of the transmit
magnetics. The TX10 path will not transmit up to the
first two Manchester encoded bits of a data
transmission, as permitted by the 802.3 Standard
RX10 Filter & RX10 Signal Detect
These blocks work in unison to remove noise and to
block signals that do not achieve the voltage levels
specified in 802.3. Signals that do not achieve the
required level are not sampled in the Clock Recovery
block and are not passed to the outputs.
When RX_DV is high, any Manchester
The synthesizer is
.
RX10 Latency
When connected to appropriate magnetics the latency
through the RX10 path is less than 6BT (600ns). This
timing is measured from the input of the receive
magnetics to the rising edge of RX_CLK. The RX10
path may ignore up to three Manchester encoded bits
at the start of data reception (802.3 allows up to 5
bits).
100Base-TX Operation
100Mb/s Data Exchange on the MII Interface
100Mb/s data is transferred across the MII with clock
speeds of 25MHz. The MAC outputs data to the
MT933 via the MII interface, on the TXD[3:0] bus.
This data is synchronised to the rising edge of TX_CLK.
To indicate that there is valid data for transmission on
the MII, the MAC sets the TX_EN signal active. This
forces the MT933 device to take in the data on the
TXD[3:0] bus and replace the first octet of the MAC
preamble with Start-of-Stream Delimiter (SSD)
symbols to indicate the start of the Physical Layer
Stream.
When the data transfer across the MII is complete,
the MAC deasserts the TX_EN signal and the MT933
adds End-of-Stream Delimiters (ESD) symbols onto
the end of the data stream. The complete data stream
(the Physical Layer Stream) is encoded from 4 bits
into 5 bits, scrambled, converted to MLT3 and driven
to the TXOP and TXON pin differentially.
The TX100 path is disabled when not in 100BASE-TX
mode and, with the exception of the RX100 Signal
Detect, the RX100 Receive Path is disabled when not
in 100BASE-TX mode.
125MHz Synthesizer
This synthesizer employs a phase-locked loop (PLL) to
generate a 125MHz timing reference from the 25MHz
reference clock. This 125MHz reference is used by the
100BASE-TX transmit function and is divided by 5 to
provide a 25MHz data strobe on TX_CLK. TX_CLK is
frequency and phase locked to the 25MHz reference
with a small phase offset. The synthesizer is disabled
when not in 100BASE-TX mode.
MT933
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