MPC8260A Motorola, MPC8260A Datasheet - Page 19

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MPC8260A

Manufacturer Part Number
MPC8260A
Description
Micro Processor
Manufacturer
Motorola
Datasheet

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1.3
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 14 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
1.3.1
Table 14 describes default clock modes for the MPC826xA.
Table 15 describes all possible clock configurations when using the hard reset configuration sequence.
Note that clock configuration changes only after POR is asserted. Note also that basic modes are shown in
boldface type.
MOTOROLA
MODCK[1–3]
000
001
010
011
100
101
110
111
Clock Configuration Modes
Local Bus Mode
CLKin
CLKin
CLKin
Figure 11 is a graphical representation of Table 13.
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
Figure 11. Internal Tick Spacing for Memory Controller Signals
Input Clock
Frequency
33 MHz
33 MHz
33 MHz
33 MHz
66 MHz
66 MHz
66 MHz
66 MHz
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
T1
T1
T1
MPC826xA (HiP4) Family Hardware Specifications
T2
CPM Multiplication
T2
T2
Table 14. Clock Default Modes
Factor
2.5
2.5
3
3
4
4
2
2
T3
T3
T3
NOTE
T4
Frequency
T4
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
166 MHz
T4
CPM
Core Multiplication
for 1:2, 1:3, 1:4, 1:5, 1:6
Factor
for 1:2.5
for 1:3.5
2.5
2.5
4
5
4
5
3
3
Clock Configuration Modes
Frequency
133 MHz
166 MHz
133 MHz
166 MHz
166 MHz
200 MHz
166 MHz
200 MHz
Core
19

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