MT8920 Zarlink Semiconductor, MT8920 Datasheet - Page 15

• Manufacturer Part Number: MT8920
• Description: 32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit
• Manufacturer: Zarlink Semiconductor

Data Sheet
Connecting the STPA to a shared ST-BUS Line
The STPA’s STo0 and STo1 outputs cannot be
directly forced into a
However, with some external logic, the STo0 output
can be buffered by a three-state device, controlled
by the STo1 output. This application is only possible
if the Tx1 RAM and associated STo1 output are not
required for some other purpose.
Figure 13 shows an external buffer U1 controlled by
the STo1 output and an external Output Data Enable
(ODE) signal. When FF (hex) is written to the Tx1
RAM, the corresponding STo1 output channel goes
to logic high. This signal, AND-ed together with a
logic high at ODE, enables U1, resulting in the STo0
signal transparently passed to the output of U1.
When 00 (hex) is written to the Tx1 RAM, the STo1
output goes logic low. This disables U1, resulting in
Parallel Port
Parallel Port
ODE
Figure 13 - Connecting STPA to a Common ST-BUS Line
high impedance
STi0
STi1
STi7
MT8920B
MT8980
STo0
STo1
STo0
STo7
STo1
ODE
state.
74HC00
a high impedance state at the output of U1,
corresponding to the selected channel.
This method of three-state buffering permits output
control on a per-channel or per-bit basis.
The ODE input is used to enable the ST-BUS outputs
after all ST-BUS devices are properly configured by
software.
contention on the ST-BUS lines during the power-up
state.
74HC125
U2
U1
This
eliminates
the
ST-BUS
MT8920B
possibility
of
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