MT8926 Zarlink Semiconductor, MT8926 Datasheet - Page 23

• Manufacturer Part Number: MT8926
• Description: T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

IRQ is an open drain interrupt output that will signal the microprocessor when an exception condition occurs (see
Figure 8 on page 18). Exception conditions are counter overflows and alarms. Interrupts are reset via the PMAC
Control Word of the CSTi1 control stream.
2.1
ANSI standards T1.403 and T1.408 define an ESF mode Facility Data Link (FDL), which is used to transport
performance information and control signals across a T1 link. The FDL channel is formed from the framing bit
position of every second frame, and therefore, has a 4 KBit/sec. bandwidth. See Table 18 on page 22 for the ESF
Framing Pattern.
The following two FDL message formats are defined in T1.403/408:
1) Bit-oriented, which are repeated 16 bit patterns or codeword messages, and
2) Message-oriented performance reports, which are LAPD protocol messages.
Bit-oriented messages (BOMs) are preemptive, and therefore, override other FDL communications. Each message
consists of a 16 bit codeword of the form 11111111 0XXXXXX0. Therefore, there are 64 unique codewords or
messages defined by XXXXXX. Refer to T1.403 or T1.408 for a list of messages and message restrictions.
BOMs are further divided into priority messages, and command and response messages. Priority messages indicate
the existence of a service-affecting failure, and are repeated until the condition that caused the message is removed.
These BOMs are transmitted for at least one second, but may be interrupted as often as once per second, for a
MT8926
22
T1.403/408 FDL Message Transfer Overview
FRAME #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
Table 18 - ESF Frame Pattern
FPS
0
0
1
0
1
1
FDL
X
X
X
X
X
X
X
X
X
X
X
X
CRC
CB1
CB2
CB3
CB4
CB5
CB6
Data Sheet
SEMICMF.019