MPC93R52 Motorola, MPC93R52 Datasheet - Page 3

• Manufacturer Part Number: MPC93R52
• Description: LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR
• Manufacturer: Motorola

TIMING SOLUTIONS
Table 1: PIN CONFIGURATION
CCLK
FB_IN
F_RANGE
FSELA
FSELB
FSELC
PLL_EN
MR/OE
QA0–4, QB0–3, QC0–1
GND
VCCA
VCC
Table 2: FUNCTION TABLE
F_RANGE
PLL_EN
Control
MR/OE
FSELA
FSELB
FSELC
Pin
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.
Default
Input
Input
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
Supply
0
0
0
0
0
0
I/O
VCO
Output divider
Output divider
Output divider
Outputs enabled (active)
Normal operation mode with PLL enabled.
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
VCC
1 (High input frequency range)
Type
4
4
2
PLL reference clock signal
PLL feedback signal input, connect to an output
PLL frequency range select
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
PLL enable/disable
Output enable/disable (high–impedance tristate) and device reset
Clock outputs
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an
external RC filter for the analog power supply pin V CCA . Please see
applications section for details.
Positive power supply for I/O and core
0
3
VCO
Output divider
Output divider
Output divider
Outputs disabled (high–impedance state) and
reset of the device. During reset, the PLL
feedback loop is open and the VCO is operating
at its lowest frequency. The MPC93R52 requires
reset after any loss of PLL lock. Loss of PLL
lock may occur when the external feedback path
is interrupted. The length of the reset pulse
should be greater than two reference clock
cycles (CCLK). The device is reset by the
internal power–on reset (POR) circuitry during
power–up.
Test mode with PLL disabled. CCLK is
substituted for the internal VCO output.
MPC93R52 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
Function
2 (Low input frequency range)
6
2
4
1
MPC93R52
MOTOROLA