MPC9447 Motorola, MPC9447 Datasheet - Page 5

• Manufacturer Part Number: MPC9447
• Description: 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
• Manufacturer: Motorola

Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17Ω (V
outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Motorola application note
AN1091.
point--to--point distribution of signals is the method of choice.
In a point--to--point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC9447 clock driver.
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 4 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9447 clock driver is effectively doubled
due to its capability to drive multiple lines at V
TIMING SOLUTIONS
CLK_STOP
IN
IN
CCLK0 or
The MPC9447 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
Q0 to Q8
Figure 4. Single versus Dual Transmission Lines
Figure 3. Output Clock Stop (CLK_STOP) Timing
CCLK1
MPC9447
MPC9447
OUTPUT
OUTPUT
BUFFER
BUFFER
17Ω
17Ω
In most high performance clock networks,
R
R
R
S
S
S
Diagram
= 33Ω
= 33Ω
= 33Ω
CC
÷2.
Z
Z
Z
Freescale Semiconductor, Inc.
O
O
O
= 50Ω
= 50Ω
= 50Ω
For More Information On This Product,
For the series
APPLICATION INFORMATION
CC
CC
=3.3V), the
Go to: www.freescale.com
=3.3V.
OutA
OutB0
OutB1
5
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases,
the drive capability of the MPC9447 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations
a delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output--to--output skew
of the MPC9447. The output waveform in Figure 5 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 33Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line.
better match the impedances when driving multiple lines, the
situation in Figure 6 “Optimized Dual Line Termination”
should be used. In this case, the series terminating resistors
The waveform plots in Figure 5 “Single versus Dual Line
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 5. Single versus Dual Line Termination
t
D
2
In
= 3.8956
OutA
V
Z
R
R
V
0
L
L
S
0
= 50Ω || 50Ω
= V
= 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
= 17Ω
= 33Ω || 33Ω
4
S
( Z
Waveforms
0
6
÷ (R
TIME (nS)
t
D
= 3.9386
OutB
S
+R
8
0
+Z
10
0
))
MPC9447
12
MOTOROLA
14
To