ADC0820BCWM National Semiconductor, ADC0820BCWM Datasheet - Page 14

• Manufacturer Part Number: ADC0820BCWM
• Description: 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function
• Manufacturer: National Semiconductor

www.national.com
2.0 Analog Considerations
2.1 REFERENCE AND INPUT
The two V
define the zero to full-scale input range of the A to D con-
verter. This allows the designer to easily vary the span of the
analog input since this range will be equivalent to the voltage
difference between V
V
of the converter can be increased (i.e., if V
LSB = 7.8 mV). The input/reference arrangement also facili-
tates ratiometric operation and in many cases the chip power
supply can be used for transducer power as well as the V
source.
This reference flexibility lets the input span not only be varied
but also offset from zero. The voltage at V
put level which produces a digital output of all zeroes.
Though V
fords nearly differential-input capability for most measure-
ment applications. Figure 13 shows some of the configura-
tions that are possible.
2.2 INPUT CURRENT
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The A/D’s sampled-data com-
parators take varying amounts of input current depending on
which cycle the conversion is in.
External Reference 2.5V Full-Scale
REF
(V
REF
REF
IN
= V
is not itself differential, the reference design af-
REF
inputs of the ADC0820 are fully differential and
(+)−V
REF
IN
DS005501-21
(+) and V
(−)) to less than 5V, the sensitivity
IN
(−). By reducing
REF
REF
(−) sets the in-
FIGURE 13. Analog Input Options
= 2V then 1
Power Supply as Reference
REF
14
DS005501-22
The equivalent input circuit of the ADC0820 is shown in Fig-
ure 14 . When a conversion starts (WR low, WR-RD mode),
all input switches close, connecting V
pacitors. Although the two 4-bit flash circuits are not both in
their compare cycle at the same time, V
capacitors at once. This is because the MS flash converter is
connected to the input during its compare interval and the LS
flash is connected to the input during its zeroing phase (Sec-
tion 1.3). In other words, the LS ADC uses V
zero-phase input.
The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5 k
to 10 k ). In addition, about 12 pF of input stray capacitance
must also be charged. For large source resistances, the ana-
log input can be modeled as an RC network as shown in Fig-
ure 15 . As R
pacitance to charge.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is the
time that WR is low. Since other factors force this time to be
at least 600 ns, input time constants of 100 ns can be ac-
commodated without special consideration. Typical total in-
put capacitance values of 45 pF allow R
out lengthening WR to give V
S
increases, it will take longer for the input ca-
Input Not Referred to GND
IN
more time to settle.
IN
to thirty-one 1 pF ca-
IN
S
to be 1.5 k
still sees all input
DS005501-23
IN
as its
with-