ADC0838 Micro Linear Corporation, ADC0838 Datasheet - Page 6

• Manufacturer Part Number: ADC0838
• Description: Serial I/O 8-Bit A/D Converters with Multiplexer Options
• Manufacturer: Micro Linear Corporation

ML2281, ML2282, ML2284, ML2288
ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the
Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be V
Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
6
SYMBOL
f
t
t
SNR
THD
IMD
t
t
t
t
t
t
C
C
CLK
ACQ
C
SET-UP
HOLD
PD1
PD0
1H
0H
IN
OUT
,
,
When the input voltage (V
0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
Cannot be tested for ML2282.
Leakage current is measured with the clock not switching.
or less.
correlation with worst-case test conditions.
Typicals are parametric norm at 25°C.
Parameter guaranteed and 100% production tested.
Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
For V
analog input voltages one diode drop below ground or one diode drop greater than the V
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog V
correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V
tolerance and loading.
minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
(f
comparator response time.
SAMPLING
IN
Clock Frequency
Sample-and-Hold Acquisition
Conversion Time
Signal to Noise Ratio
ML2281
Total Harmonic Distortion
ML2281
Intermodulation Distortion
ML2281
Clock Duty Cycle
CS Falling Edge or Data Input (Note 4)
Valid to CLK Rising Edge
Data Input Valid after
CLK Rising Edge
CLK Falling Edge to Output
Data Valid
Rising Edge of CS to Data
Output and SARS Hi-Z
Capacitance of Logic Input
Capacitance of Logic Outputs
– V
IN
95kHz); ML2288 V
+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
PARAMETER
IN
) at any pin exceeds the power supply rails (V
IN
= 30kHz, 5V sine (f
(Note 4)
Not including MUX adddressing time
V
(f
nonfundamental components up to 1/2
of f
V
(f
3, 4, 5 harmonics relative to fundamental
(Note 11)
V
f
(f
(f
(f
(Notes 4, 10)
(Note 4)
C
Data MSB first
Data LSB first
C
test circuits) (Note 5)
C
B
SAMPLING
SAMPLING
SAMPLING
A
A
IN
IN
IN
L
L
L
= 39.8kHz, 2.5V Sine, f
SAMPLING
– f
– 2f
= 100pF (Note 4 & 12)
= 10pF, R
= 100pF, R
= f
= 40kHz, 5V sine. f
= 40kHz, 5V sine. f
B
SAMPLING
A
), (2f
B
) relative to fundamental (Note 11)
+ f
(Continued)
B
A
. f
120kHz). IMD is (f
120kHz). THD is sum of 2,
L
120kHz). Noise is sum of all
(Note 11)
+ f
A
L
CONDITIONS
= 10k (see high impedance
89kHz).
= 40kHz, 2.5V sine.
B
= 2k (Note 4)
), (2f
IN
A
IN
< GND or V
– f
CLK
CLK
or V
CLK
IN
B
), (f
= 34kHz, 5V sine (f
REF
= 1.333MHz
= 1.333MHz
= 1.333MHz
A
A
does not exceed the supply voltage by more than 50mV, the output code will be
+ 2f
+ f
IN
CC
> V
B
supply. Be careful, during testing at low V
B
),
),
CC
) the absolute value of current at that pin should be limited to 25mA
SAMPLING
MIN
130
10
40
80
102kHz); ML2284 V
DC
NOTE 3
over temperature variations, initial
TYP
–60
–60
1/2
47
90
50
40
80
5
5
8
IN
CC
= 32kHz, 5V sine
levels (4.5V), as high level
1.333
MAX
200
110
160
60
90
UNITS
LIMIT
1/f
1/f
kHz
dB
dB
dB
pF
pF
%
ns
ns
ns
ns
ns
ns
CLK
CLK