ADCV08832CIM National Semiconductor, ADCV08832CIM Datasheet - Page 3

• Manufacturer Part Number: ADCV08832CIM
• Description: Low Voltage/ 8-Bit Serial I/O CMOS A/D Converter with Sample/Hold Function
• Manufacturer: National Semiconductor

C
t
t
t
t
t
t
C
C
f
SNR
THD
SINAD
ENOB
SFDR
CONV
ca
SET-UP
HOLD
pd1
1H
S
The following specifications apply for V
limits apply for T
Symbol
The following specifications apply for V
non-coherent 2048 samples.
Symbol
IN
IN
OUT
Electrical Characteristics
Dynamic Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND = 0 V
Note 4: When the input voltage V
maximum package input current rating limits the number of pins that can safely exceed V
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k
Note 7: Typical are at T
Note 8: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 10: For V
forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V
analog inputs (e.g., 3.3V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode; this means that as long as the analog V
will be correct. Exceeding the range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
Note 11: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (3.3V
is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases
considered for determining the on channel leakage current are the same except total current flow through the selected channel is measured.
Note 12: A 40% to 60% duty cycle range insures proper operation at all clock frequencies.
Note 13: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator
response time.
voltage range will therefore require a minimum supply voltage of 3.25 V
, t
, t
0H
pd0
Clock Duty Cycle
(Note 12)
Conversion Time (Not Including MUX
Addressing Time)
Acquisition Time
Set Up Time Required from Falling CS
to Rising Clock Edge
Data Input Valid after CLK
Rising Edge
CLK Falling Edge to Output
Data Valid (Note 13)
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
Input Capacitance of CH
(Note 14)
Input Capacitance of CLK, D1
Output Capacitance of Logic Outputs
D0 (in TRI-STATE)
Sampling Rate
Signal-to-Noise Ratio (Note 16)
Total Harmonic Distortion (Note 17)
Signal-to-Noise and Distortion
Effective Number Of Bits (Note 15)
Spurious Free Dynamic Range
IN(−)
A
V
J
IN(+)
= T
= 25˚C and represent the most likely parametric norm.
J
the digital output will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will
= T
Parameter
Parameter
IN
at any pin exceeds the power supplies (V
MIN
to T
0
MAX
, CH
CC
CC
; all other limits T
D
1
= 3.3V, 50% Duty Cycle, and t
= 3.3V, f
= (T
(Continued)
JMAX
DC
− T
CLK
, unless otherwise specified.
A
)/
f
C
Data MSB First
Data LSB First
C
(see TRI-STATE Test Circuit)
= 500 kHz, T
CLK
JA
DC
L
L
DC
) and the remaining off channel tied low (0 V
A
= 100 pF:
= 100 pF, R
or the number given in the Absolute Maximum Ratings, whichever is lower.
over temperature variations, initial tolerance and loading.
= 500 kHz
IN
= T
resistor. The machine mode is a 200 pF capacitor discharged directly into each pin.
<
3
J
(GND) or V
Conditions
Conditions
= 25˚C.
A
IN
= 25˚C, R
does not exceed the supply voltage by more than 50 mV, the output code
L
CC
= 10 k
IN
r
with an input current of 5 mA to four pins.
= t
>
V
f
CC
= 20 ns unless otherwise specified. Boldface
SOURCE
,) the current at that pin should be limited to 5 mA. The 20 mA
JMAX
CC
. During testing at low V
,
JA
= 25 , f
and the ambient temperature, T
Typical
Typical
f
CLK
−67.6
49.5
49.4
DC
−66
7.9
35
13
5
5
), total current flow through the off channel
/13
IN
= 9.6 kHz, V
CC
Limits
Limits
levels (e.g., 2.7V), high level
150
100
40
60
16
15
20
1
8
⁄
2
DC
IN
to 3.30 V
A
= 3.3V
. The maximum
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1/f
ns (max)
ns (max)
% (max)
ns (min)
ns (min)
% (min)
CLK
1/f
Units
Units
ksps
DC
Bits
P-P
pF
pF
pF
dB
dB
dB
dB
µs
ns
CLK
(max)
input
,