NJU3430 NJR Corporation, NJU3430 Datasheet - Page 11

• Manufacturer Part Number: NJU3430
• Description: 16-Character 1-Line Dot Matrix VFD Contorller Driver
• Manufacturer: NJR Corporation

(h)RAM Address Set
(h)RAM Address Set
address and Display position are shown below :
address and Display position are shown below :
(i)Write Data to RAM
(i)Write Data to RAM
used that is set the address just before writing data. Therefore, when the new data writing, the address set should
used that is set the address just before writing data. Therefore, when the new data writing, the address set should
be executed before writing data. The address is increased by 1 automatically after writing data, therefore, the MPU
be executed before writing data. The address is increased by 1 automatically after writing data, therefore, the MPU
writes the data into the each RAM without any address setting after the start address.
writes the data into the each RAM without any address setting after the start address.
The DD RAM, MK RAM and CG RAM Address are set by RAM Address Set. Correspondences of each RAM
The DD RAM, MK RAM and CG RAM Address are set by RAM Address Set. Correspondences of each RAM
The data are written into DD RAM, MK RAM and CG RAM by Write Data to RAM. The writing data address is
The data are written into DD RAM, MK RAM and CG RAM by Write Data to RAM. The writing data address is
The writing data in the each RAM are shown below.
The writing data in the each RAM are shown below.
(Writing example)
(Writing example)
Correspondence of DD RAM Address and Timing terminals (Not shift)
Correspondence of DD RAM Address and Timing terminals (Not shift)
Correspondence of MK RAM Address and Timing terminals (Not shift)
Correspondence of MK RAM Address and Timing terminals (Not shift)
About the detail of CG RAM Address, refer to "(1)CG RAM data and Character Dot Matrix”.
About the detail of CG RAM Address, refer to "(1)CG RAM data and Character Dot Matrix”.
DD RAM Address
DD RAM Address
DD RAM Data[SD7 to SD0]
DD RAM Data[SD7 to SD0] --- Character code of each digit
MK RAM Data[SM1 to SM0]
MK RAM Data[SM1 to SM0] --- Icon display of each digit
CG RAM Data[SC4 to SC0]
CG RAM Data[SC4 to SC0] --- Character code
DD RAM Address 00
MK RAM Address 00
R S
R S
0
1
10000011
10000011
set(03)
set(03)
1Byte
1Byte
Digits
Digits
S D 7 S D 6 S D 5 S D 4 S D 3 S D 2 S D 1 S D 0
B 7
B 7
1
1
1
0
0
H H
B 6
B 6
0
0
1
0
0
1
1
A C 5 A C 4 A C 3 A C 2 A C 1 A C 0
DD RAM Address(03)
DD RAM Address(03)
B 5
01
01
B 5
2
2
0
0
0
0
set CG ROM(55)
set CG ROM(55)
02
02
3
3
S C 4 S C 3 S C 2 S C 1 S C 0
01010101
01010101
B 4
B 4
2Byte
2Byte
0
1
0
03
03
--- Character code of each digit
--- Icon display of each digit
--- Character code
4
4
(About the detail, refer to "(1)CG RAM data and Character Dot Matrix”.)
(About the detail, refer to "(1)CG RAM data and Character Dot Matrix”.)
A M 3 A M 2 A M 1 A M 0
A D 3 A D 2 A D 1 A D 0
B 3
04
04
B 3
5
5
0
05
05
H H
6
6
B 2
B 2
0
H H
06
06
7
7
DD RAM Address(04)
DD RAM Address(04)
S M 1 S M 0
07
07
B 1
B 1
8
8
set CG ROM(F8)
set CG ROM(F8)
08
08
9
9
11111000
11111000
B 0
B 0
3Byte
3Byte
09
10
09
10
0A
0A
11
11
DD RAM Addredd Set:(00)
DD RAM Addredd Set:(00)
MK RAM Address Set:(00)
MK RAM Address Set:(00)
CG RAM Address Set:(00)
CG RAM Address Set:(00)
DD RAM Data Set:(00)
DD RAM Data Set:(00)
MK RAM Data Set:(00)
MK RAM Data Set:(00)
CG RAM Data Set:(00)
CG RAM Data Set:(00)
0B
0B
12
12
H H
H H
: (00)
: (00)
: SM1
: SM1 MK
: (00)
: (00)
0C
0C
13
13
DD RAM Address(05)
DD RAM Address(05)
set CG ROM(35)
set CG ROM(35)
0D
0D
14
14
H H
H H
to (FF)
to (FF)
to (0F)
to (0F)
00110101
00110101
MK
4Byte
4Byte
0E
15
0E
15
NJU3430
NJU3430
2 2
, SM0
, SM0 MK
0F
0F
H H
16
16
H H
Dot Data
Dot Data
H H
H H
H H
to (FF)
to (FF)
to (1F)
to (1F)
to (03)
to (03)
H H
H H
H H
H H
MK
to (0F)
to (0F)
H H
to (3F)
to (3F)
to (0F)
to (0F)
1 1
H H
H H
H H
H H
H H
H H