TS68040 ATMEL Corporation, TS68040 Datasheet - Page 31

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

TS 68040
6.4.3 - Cache instructions
The TS 68040 supports the following instructions for cache maintenance. Both instructions may selectively operate on the
data or instruction cache.
CINV : Invalidates a single line, all lines in a physical page, or the entire cache.
CPUSH : Pushes selected dirty data cache lines to memory, then invalidates all selected lines.
6.5 - Operand transfer mechanisms
The TS 68040 external synchronous bus supports multiple masters and overlaps arbitration with data transfers. The bus is
optimized to perform high-speed transfers to and from an external cache or memory. The data and address buses are each
32 bits wide.
6.5.1 - Transfer types
The TS 68040 provides two signals (TT1-TT0) that define four types of bus transfers : normal access, MOVE16 access,
alternate access, and interrupt acknowledge access. Normal accesses identify normal memory references : MOVE16 accesses
are memory accesses by a MOVE16 instruction ; and alternate accesses identify accesses to the undefined address spaces
(function code values of 0, 3, 4, 7). The interrupt acknowledge access is used to fetch an interrupt vector during interrupt
exception processing.
6.5.2 - Burst transfer operation
During burst read write to cache transfers, the values on the address and transfer type signals do not change ; they are the
address of the first requested item of the cache line. When the TS 68040 request a burst read transfer of a cache line, the
address bus indicates the address of the long word in the line needed first, but the memory system is expected to provide
data in the following order (modulo 4) : 0, 1, 2, 3 (long-word offsets). The first address needed may not be from offset 0 ;
nevertheless, all four long words must be transferred. Burst writes occur in a similar manner.
6.5.3 - Bus snooping
Bus snooping ensures that data in main memory is consistent with data in the on-chip caches. If an alternate bus master
is performing a read transfer on the bus and snooping is enabled, and if the snoop logic determines that the on-chip data
cache has dirty data (data valid but not consistent with memory) for this transfer, ther memory is prevented from responding
to the read request, and the TS 68040 supplies the data directly to the master. If the alternate master is performing a write
transfer on the bus and snooping is enabled, and if the snooper determines that one of the on-chip caches has a valid line
for this request, then the snooper may either invalidate or update the line as selected by the snoop control signals.
6.6 - Exception processing
The TS 68040 provides the same extensions to the exception stacking process as the TS 68030. If the M bit in the status
register is set, the master stack pointer is used for all task-related exceptions. When a nontask-related exception occurs (i.e.,
an interrupt), the M bit is cleared, and the interrupt stack pointer is used. This feature allows a task’s stack area to be carried
within a single processor control block, and new tasks may be initiated by simply reloading the master stack pointer and
setting the M bit.
The externally generated exceptions are interrupts, bus errors, and reset conditions. The interrupts are requests from external
devices for processor action ; whereas, the bus error and reset signals are used for access control and processor initialization.
The internally generated exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPVcc, FTRAPcc, CHK, CHK2, and DIV instructions can all generate exceptions as part of their instruction execution.
Tracing behaves like a very high-priority, internally generated interrupt whenever it is processed. The other internally generated
exceptions are caused by unimplemented floating-point instructions, illegal instructions, instruction fetches from odd addres-
ses, and privilege violations. Finally, the MMU can generate exceptions, for access violations and for when invalid descriptors
are encountered during table searches.
Exception processing for the TS 68040 occurs on the following sequence :
1 - an internal copy is made of the status register,
2 - the vector number of the exception is determined,
3 - current processor status is saved,
4 - the exception vector offset is determined by multiplying the vector number by four.
This offset is then added to the contents of the VBR to determine the memory address of the exception vector. The instruction
at the address given in the exception vector is fetched, and normal instruction decoding and execition is started.
6.7 - Memory management units
The full addressing range of the TS 68040 is 4 Gbytes (4,294,967,296 bytes). However, most TS 68040 systems implement
a much smaller physical memory. Nonethless, by using virtual memory techniques, the system can be made to appear to
have a full 4 Gbytes of physical memory available to each user program. The independent instruction and data MMUs fully
support demandpaged virtual-memory operating systems with either 4K or 8K page sizes. In addition to its main function of
memory management, each MMU protects supervisor areas from accesses by user programs and also provides write pro-
tection on a page-by-page basis. For maximum efficiency, each MMU operates in parallel with other processor activities.
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