TS83102G0B ATMEL Corporation, TS83102G0B Datasheet - Page 36

• Manufacturer Part Number: TS83102G0B
• Description: 10-bit 2 GSPS ADCthis State-of-the-art 10-bit 2 GSPS Converter Offers an Unprecedented Bandwidth of 3.3 GHZ And Excellent Band Flatness, Allowing to Directly Digitize Very High if Signals (2nd And 3rd Nyquist Zones) With High Linearity : The SFDR Rem
• Manufacturer: ATMEL Corporation

Table 5. Definitions of Terms (Continued)
36
PSRR
SFDR
SINAD
SNR
SSBW
TA
TC
TD1
TD2
TF
THD
TOD
TPD
TR
TRDR
TS
VSWR
TS83102G0B
Power Supply
Rejection Ratio
Spurious Free
Dynamic Range
Signal to Noise and
Distortion Ratio
Signal to Noise Ratio
Small Signal Input
Bandwidth
Aperture Delay
Encoding Clock
Period
Time Delay from Data
to Data Ready
Time Delay from Data
Ready to Data
Fall Time
Total Harmonic
Distortion
Digital Data
Output Delay
Pipeline Delay
Rise Time
Data Ready Reset
Delay
Settling Time
Voltage Standing
Wave
PSRR is the ratio of input offset variation to a change in power supply voltage
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the next highest spectral component (peak spurious spectral component).
SFDR is the key parameter for selecting a converter to be used in a frequency domain
application (radar systems, digital receiver, network analyzer...). It may be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (i.e. always related back to converter
full-scale)
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components, including the harmonics except DC
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first five harmonics
Analog input frequency at which the fundamental component in the digitally reconstructed
output waveform has fallen by 3 dB with respect to its low frequency value (determined by
FFT analysis) for input at full-scale -10 dB (-10 dBFS)
The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing
point), and the time at which (V
TC1 = minimum clock pulse width (high) TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
Time delay for the output data signals to fall from 80% to 20% of delta between low level and
high level
The ratio expressed in dBc of the RMS sum of the first five harmonic components, to the
RMS value of the measured fundamental spectral component
The delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing
point) to the next point of change in the differential output data (zero crossing) with a
specified load
The number of clock cycles between the sampling edge of an input data and the associated
output data being made available (not taking in account the TOD). For the JTS8388B the
TPD is 4 clock periods
Time delay for the output data signals to rise from 20% to 80% of delta between the low level
and high level
Delay between the falling edge of the Data Ready output asynchronous Reset signal
(DDRB) and the reset to digital zero transition of the Data Ready output signal (DR)
Time delay to achieve 0.2% accuracy at the converter output when an 80% full-scale step
function is applied to the differential analog input
mismatching between the packaged ADC input impedance (ideally 50 Ω or so) and the
transmission line’s impedance. The packaged ADC input impedance (transmission line and
termination) is controlled so as to ensure VSWR < 1.2 :1 from DC up to 2.5 GHz. A VSWR of
1.2 :1 corresponds to a 0.039 dB insertion loss (20 dB return loss) - i.e. 99% power
transmitted and 1% reflected
VSWR
=
(
1
+
S
11
)
÷
(
1 S
–
11
)
IN
matrix. The VSWR over frequency measures the degree of
Where S11 is the reflection coefficient of the scattering
, V
INB
) is sampled
2101C–BDC–02/04