NSBMC096 National Semiconductor Corporation, NSBMC096 Datasheet - Page 5

• Manufacturer Part Number: NSBMC096
• Description: Burst Memory Controller
• Manufacturer: National Semiconductor Corporation

A(A B)0–11
RAS(A B)0 –3
CAS(A B)0–3
MWE(A B)
REFRESH
TX(A B)
LE(A B)
Pin Descriptions
MEMORY INTERFACE
The NSBMC960 is designed to drive a memory array orga-
nized as 2 leaves each of 32 bits The address and control
signals for the memory array are output through high current
BUFFER CONTROLS
Buffer control signals are provided to simplify the control of
the interface between the DRAM and i960 data busses
Pin
Pin
Data Bus Transmit A and B (Output Active Low) These outputs are multi-function signals The signal names
as they appear on the logic symbol are the default signal names (Mode
control buffer output enables during data read transactions and in effect control the multiplexing of data from
each memory leaf onto the i960 CA CF data bus
Data Bus Latch Enable A and B (Output Active Low) These outputs are mode independent however the
timing of the signals change for different operational modes They control transparent latches that hold data
transmiffed during a write transaction In modes 0 and 1 the latch controls follow the timing of CAS for each
leaf while in modes 2 and 3 the timing of LEA and LEB is shortened to
Multiplexed Address Bus (Output 24 mA) These two buses transfer the multiplexed row and column
addresses to the memory array leaves A and B When non-interleaved operation is selected only address bus A
should be used
Row Address Strobes (Output 12 mA Active Low) These strobes indicate the presence of a valid row
address on busses A(A B)0–11 These signals are to be connected one to each leaf of memory Four banks of
interleaved memory may be attached to a NSBMC960
Column Address Strobe (Output 12 mA Active Low) These strobes latch a column address from A(A B)0–
11 They are assigned one to each byte in a leaf
Memory Write Enable (Output 24 mA Active Low) These are the DRAM write strobes One is supplied for
each leaf to minimize signal loading
Refresh in progress (Output 12 mA Active Low) This output gives notice that a refresh cycle is to be
executed The timing leads refresh RAS by one cycle
(Continued)
5
Description
Description
drivers in order to minimize propagation delay due to input
impedance and trace capacitance External array drivers
are not required The address and control signals however
should be externally terminated
Multiple operating modes facilitate choice of buffer type
and simple bus buffers (‘‘245’’s) bus latches (‘‘543’’s) and
bus registers (‘‘646’’s) are all supported
e
clock
0) The purpose of these outputs is to