SDA9188-3X Infineon Technologies Corporation, SDA9188-3X Datasheet - Page 17

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SDA9188-3X

Manufacturer Part Number
SDA9188-3X
Description
Picture-in-picture Processor With On-chip PLL
Manufacturer
Infineon Technologies Corporation
Datasheet

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Register 6 (Address 06
Bit
d4:d0
d5
d6
d7
Semiconductor Group
Function
Setting the delay of VSI
(see test circuit 6)
0 = Vertical noise reduction inactive
1 = Vertical noise reduction active
0 = Check for correct TV standard inactive
1 = Check for correct TV standard active
0 = Field display
1 = Frame display
H
)
17
Name
VSIDEL
VSIS
STATI
FRAME
Remarks
Setting is possible in steps
of 2,37 s (see
measurement circuit 6)
Noise reduction of the VSI
pulse (should be set to ‘1’
under normal conditions.)
If the check is active a full
frame display is only
possible if the number of
lines is exactly according
the TV standard:
312.5 (50 Hz)
262.5 (60 Hz)
Only active if the line
number and the interlace
mode are equal for both
inset and parent signal.
If the display mode is 100/
120 Hz or progressive
scan d7 has to be set to 0
SDA 9188-3X

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