SDA9205-2 Infineon Technologies Corporation, SDA9205-2 Datasheet
SDA9205-2
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SDA9205-2 Summary of contents
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Triple 8-Bit Analog-to-Digital-Converter Preliminary Data Features Three equivalent CMOS A/D converters on chip 30-MHz sample rate 8-bit resolution No external sample & hold required On-chip input buffer for each analog channel Internal clamping circuits for each of the ADCs Different ...
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Pin Configuration (top view) Semiconductor Group 2 SDA 9205-2 ...
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Pin Definitions and Functions Pin No. Symbol Function Digital outputs of ADC C (port C) C0 least significant bit 3 V Output stages supply ground of port C QGNDC 4 UFLC Underflow data output ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Function 44 OENB Output enable of port B 45 UFLB Underflow data output of ADC B 46 OFLB Overflow data output of ADC Output stages supply ground of port ...
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Circuit Description Analog to Digital Converter The SDA 9205-2 implements 3 independent 8-bit analog-to-digital converters. They are two step converters with a coarse comparator block and two fine comparator blocks each using pipeline architecture for high speed sampling performance. During ...
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The external clamping capacitance is loaded by on chip current sources (typ. 200 A) during clamping. So the loading time depends on the values of The loading time for a complete loading cycle is 1200 CLK pulses typical (44 s ...
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Digital Signal Processing The digital signal processing block performs averaging of sampled data. The , , represent the results of DSP function with input data from 8-bit busses. A special DSP function in combination with a special ...
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The following DSP functions are available (1. – 3 (1. – 4 (2. – 3 (2. – 4 ...
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Figure 3 DSP Function Detailed function of DSP block is shown in figure 3. Semiconductor Group 9 SDA 9205-2 ...
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Output Coding Eight different digital output multiplex formats are available. They are selectable via four control lines CONT0 … CONT3. These multiplexed formats perform combinations of DSP functions of the several converters (A, B, C). DSP functions – output coding ...
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The digital output data are synchronized by the FSY signal. The first high of FSY defines the first output format byte and is synchronized to CLK. In case of asynchronism the first (in formats 8:1:1, 4:1:1 the first and the ...
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Format 8:8:8 DSP Function CONT3 1.0 + 2.0 0 1.1 + 2.1 0 Port Bit Data ...
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Format 8:4:4 DSP Function CONT3 1.0 + 2.0 0 1.1 + 2.1 0 Port Bit Data ...
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Format 8:2:2 DSP Function CONT3 1.0 + 2.0 0 1.1 + 2.2 0 Port Bit Data ...
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Format 8:1:1 DSP Function CONT3 1.0 + 2.0 0 1.1 + 2.3 0 Port Bit Data ...
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Format 4:8:8 DSP Function CONT3 1.0 + 2.0 1 1.1 + 2.1 1 Port Bit Data ...
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Format 4:4:4 DSP Function CONT3 1.0 + 2.0 1 1.1 + 2.1 1 Port Bit Data ...
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Format 4:2:2 DSP Function CONT3 1.0 + 2.0 1 1.1 + 2.2 1 Port Bit Data ...
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Format 4:1:1 DSP Function CONT3 1.0 + 2.0 1 1.1 + 2.3 1 Port Bit Data ...
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Output Coding for Binary/Two’s Complement Mode Binary or two’s complement output coding is selectable for each separate output port ( via control inputs DTA, DTB, DTC. This coding is independent from selected formats (8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, ...
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Table 2 Output Coding for Format 4:2:2 V Table 2 is valid for = 0.5 V and REFL Step VIN Converter A V Underflow < – 0.125 – 0.125 – 0.117 V ...
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Block Diagram Absolute Maximum Ratings Parameter Supply voltages 1) Input voltage range all inputs Ambient temperature Storage temperature 1) All voltage values are with respect to network ground terminal Semiconductor Group Symbol Limit Values min ...
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Characteristics MHz, all specifications min ( CLK Parameter Symbol Power Requirements V Analog supply voltage CC V Digital supply voltage DD V Output stage supply ...
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Characteristics (cont’ MHz, all specifications min ( CLK Parameter Symbol Digital Inputs V L-input voltage IL V H-input voltage IH Input current I I Digital ...
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Characteristics (cont’ MHz, all specifications min ( CLK Parameter Symbol Timing (see figure 5) t Output data delay time QD t Output data hold time ...
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Sample output data-delay is shown on format 8:8:8 with DSP function 1.0 + 2.0 Figure 6 Diagram of Complete Timing There is a delay of 9 clock cycles between sampling of an analog input signal and the corresponding digital output ...
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Figure 7 SNR Typ. (without harmonics) versus Analog Frequency (411 Mode DSP 1.0) References Figure 8 Blocking the SDA 9205-2 Capacitors: 100 nF - Ceramic Tantal Elko Semiconductor Group 27 SDA 9205-2 ...
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Grounding Figure 8 (cont’d) Blocking the SDA 9205-2 Semiconductor Group 28 SDA 9205-2 ...
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Chip Capacitors 100 nF (as near as possible to the socket) Figure 8 (cont’d) Blocking the SDA 9205-2 Semiconductor Group 29 SDA 9205-2 ...
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Figure 9 Application Circuit 1 (4:1:1 Format, for Siemens Featurebox) Semiconductor Group 30 SDA 9205-2 ...
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Figure 10 Application Circuit 2 (4:1:1 Format, for General Application) Semiconductor Group 31 SDA 9205-2 ...