SDA9220-5 Infineon Technologies Corporation, SDA9220-5 Datasheet - Page 5

• Manufacturer Part Number: SDA9220-5
• Description: Memory SYNC Controller Iii
• Manufacturer: Infineon Technologies Corporation

Device Interfaces
The interfaces of this device are designed to work with the CSG SDA 9257 and triple ADC
SDA 9205-2, or DMSD/CGC, the TV-SAMs SDA 9251-2X and Picture Processor SDA 9290-5. The
standard conversion function can be enabled and disabled on one pin. All other functions are set on
an I
I
1. Functional Overview
Semiconductor Group
2
C Bus Interface
When switching from free running to line-locked mode, the following maximum synchronization
times can occur for standard signals:
a) Vertical synchronization at
a) Horizontal synchronization at
The following control signals are received on the I
– Synchronization (EXSYN)
– Blanking (BLK)
– Control for frame mode (MUXI, MUXS)
– VS noise reduction (VNR)
– 50/60-Hz standard (VERT)
– Deflection raster (VDM 1-0)
– Field mode with field changeover (FLDM, FLDC, FLDF)
– Delay compensation for write channel (WDEL 4-0)
– Still (STB)
– Frame (FR)
– Write mode (WM 1-0)
– Picture position for 9-image, picture-in-picture (VPOS 1-0, HPOS 1-0)
– Zoom mode (ZM)
– Position of zoom detail (ZV 2-0, ZH 3-0)
– NTSC mode with 864 pixels per line (N864)
– HS2 phase relation (HP 6-0)
– Disabling of frame display signal (FRDIS)
– Delay of frame display signal (FRD 6-0)
– Duration of CFH signal (CFHW 3-0)
– Position of CFH signal (CFHP 3-0)
2
C Bus interface.
50 (60) Hz and 100 (120) Hz:
50 (60) Hz:
100 (120) Hz:
220 (183) ms
100 (83) ms
100 (75) ms
121
2
C Bus:
SDA 9220-5