SDA9362 Infineon Technologies Corporation, SDA9362 Datasheet - Page 13

• Manufacturer Part Number: SDA9362
• Description: Ddc-plus-deflection Controller
• Manufacturer: Infineon Technologies Corporation

2.3
The circuit is only completely reset at power-on/off (timing diagram refer 5.3). If the pin
RESN has L-level or during standby operation some parts of the circuit are not affected
(timing diagram refer 5.4):
HD output
H-protection
V-protection
SCL)
01
00
Status bit PONRES
V
V
CPU
1)
2)
Note: Power-On-Reset state is deactivated after ca. 32 cycles of the X1/X2 oscillator
2.4
H
31.25 kHz
31.5 kHz
The allowed deviation of all input line frequencies is max. ± 4.5 %.
n
I:
NI:
Semiconductor Group
2
2
2
L
REFP
REFH
C Interface (SDA,
C Register
C Register
:
H
H
Inactive if HPROT < V2 (typ. 2.4 V)
Can only be read after Power-On-Reset is finished
..1B
, 48
,
clock. RESN = Low and standby state are deactivated after ca. 42 cycles of the
CLL clock.
Number of lines per frame
Interlaced
Non interlaced
V
Reset Modes
Frequency Ranges
H
H
REFL
Power-On-Reset
High
Inactive
Inactive
Tristate
Set to default values Set to default values Set to default values
Set to default values Not affected
Set to 1
Not affected
Not affected
Inactive
V
50 Hz
100 Hz
60 Hz
120 Hz
2)
13
Active
Active
External Reset
(pin RESN=0)
Active
Ready
Set to 1
Not affected
Not affected
Inactive
1)
n
625 NI / 1250I
625 I
525 NI / 1050 I
525 I
L
Standby Mode
( I
Active
Active
Active
Ready
Not affected
Not affected
Not affected
Inactive
Inactive
2
C-Bit STDBY=1)
1)
SDA 9362
1998-02-01