SDA9380 Micronas Intermetall GmbH, SDA9380 Datasheet - Page 21
SDA9380
Manufacturer Part Number
SDA9380
Description
Enhanced Deflection Controller And RGB Video Processor (EDDC)
Manufacturer
Micronas Intermetall GmbH
Datasheet
1.SDA9380.pdf
(72 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SDA9380
Manufacturer:
MICRONAS
Quantity:
20 000
Company:
Part Number:
SDA9380GEG
Manufacturer:
SMK
Quantity:
382
SDA 9380 - B21
5.3
The circuit is only completely reset at power-on/off (timing diagram ref. 11.3). If the pin RESN has L-
level or during standby operation some parts of the circuit are not affected (timing diagram ref. 11.4):
Note:
5.4
The allowed deviation of all input line frequencies is max.
n
Micronas
HD output
H-protection
V-protection
IIC-Interface (SDA, SCL)
IIC-Register 01..1C
IIC-Register 00, 1D...30h
Status bit PONRES
VREFH
CPU
L
:
number of lines per frame
Reset modes
Frequency ranges
1)
2)
Power-On-Reset state is deactivated after ca. 32768 cycles of the X1/X2 oscillator clock.
RESN=Low and standby state are deactivated after ca. 42 cycles of the CLL clock.
*) only with internal clock generation
: inactive if HPROT < V2 (typ. 1.5V)
: can only be read after Power-On-Reset is finished
15.625 kHz
18.75 kHz*
33.75 kHz*
15.75 kHz
31.25 kHz
31.5 kHz
35 kHz*
38 kHz*
H
set to default values
set to default values
Power-On-Reset
not affected
set to 1
inactive
inactive
inactive
tristate
High
66.7 Hz
100 Hz
120 Hz
2)
50 Hz
60 Hz
60 Hz
50 Hz
60 Hz
70 Hz
60 Hz
60 Hz
72 Hz
5-13
V
set to default values
625 I
525 I
625 I
625 NI / 1250 I
625 I
525 NI / 1050 I
449 NI
525 I
1125 I
525 NI
632 NI
525 NI
±
4.5%.
External Reset
(pin RESN=0)
not affected
not affected
inactive
active
set to 1
n
active
active
ready
L
1)
Preliminary Data Sheet
System description
set to default values
(I
2
Standby mode
C bit STDBY=1)
not affected
not affected
active
inactive
inactive
active
active
ready
2001-05-03
1)