PIC16LC72 Microchip Technology, PIC16LC72 Datasheet - Page 72
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PIC16LC72
Manufacturer Part Number
PIC16LC72
Description
8-Bit CMOS Microcontrollers
Manufacturer
Microchip Technology
Datasheet
1.PIC16LC72.pdf
(124 pages)
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PIC16C72 Series
FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
10.14
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
10.15
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
10.16
PIC16CXXX family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, DS30277.
DS39016A-page 72
Note 1:
Note:
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT(4)
2:
3:
4:
INT pin
OSC1
Program Verification/Code Protection
ID Locations
PC
In-Circuit Serial Programming™
XT, HS or LP oscillator mode assumed.
T
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
Microchip does not recommend code pro-
tecting windowed devices.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
(drawing not to scale) This delay will not be there for RC osc mode.
Q1 Q2 Q3 Q4
Inst(PC + 1)
SLEEP
PC+1
Q1
Processor in
SLEEP
PC+2
Preliminary
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
PC+2
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
Q1 Q2 Q3 Q4
1998 Microchip Technology Inc.
Inst(0004h)
Dummy cycle
0004h
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h