BC41B143A-ds-003Pc CSR, BC41B143A-ds-003Pc Datasheet - Page 71

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BC41B143A-ds-003Pc

Manufacturer Part Number
BC41B143A-ds-003Pc
Description
Blue Core ROM Plug-n-Go
Manufacturer
CSR
Datasheet
10.7.8 PCM Timing Information
BC41B143A-ds-003Pc
Symbol
f
-
t
t
-
t
t
t
t
t
t
t
t
mclk
mclkh
mclkl
dmclksynch
dmclkpout
dmclklsyncl
dmclkhsyncl
dmclklpoutz
dmclkhpoutz
supinclkl
hpinclkl
(a)
(a)
(a)
Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are
reduced.
Parameter
PCM_CLK frequency
PCM_SYNC frequency
PCM_CLK high
PCM_CLK low
PCM_CLK jitter
Delay time from PCM_CLK high to PCM_SYNC
high
Delay time from PCM_CLK high to valid
PCM_OUT
Delay time from PCM_CLK low to PCM_SYNC
low (Long Frame Sync only)
Delay time from PCM_CLK high to PCM_SYNC
low
Delay time from PCM_CLK low to PCM_OUT
high impedance
Delay time from PCM_CLK high to PCM_OUT
high impedance
Set-up time for PCM_IN valid to PCM_CLK low
Hold time for PCM_CLK low to PCM_IN invalid
© Cambridge Silicon Radio Limited 2005
Table 10.8: PCM Master Timing
4MHz DDS
generation. Selection
of frequency is
programmable. See
Table 10.10.
48MHz DDS
generation. Selection
of frequency is
programmable. See
Table 10.11 and
PCM_CLK and
PCM_SYNC
Generation on page
75.
4MHz DDS generation
4MHz DDS generation
48MHz DDS
generation
Advance Information
Min
980
730
2.9
30
10
-
-
-
-
-
-
-
-
Typ
128
256
512
8
-
-
-
-
-
-
-
-
-
-
Device Terminal Descriptions
Max
21
20
20
20
20
20
20
-
-
-
-
-
Page 71 of 94
ns pk-pk
Unit
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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