APL5930 Anpec Electronics Corporation, APL5930 Datasheet - Page 12
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APL5930
Manufacturer Part Number
APL5930
Description
3a, Ultra Low Dropout 0.23v Typical Linear Regulator
Manufacturer
Anpec Electronics Corporation
Datasheet
1.APL5930.pdf
(16 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
APL5930QBI-TRG
Manufacturer:
ANPEC/茂达电子
Quantity:
20 000
APL5930
Layout Consideration
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Connect one pin of the C1 to the VOUT pin for reli-
Copyright
Rev. A.1 - Jun., 2008
Please solder the Exposed Pad on the VIN pad on
Please place the input capacitors for VIN and VCNTL
Ceramic decoupling capacitors for load must be
To place APL5930 and output capacitors near the
The negative pins of the input and output capacitors
Large current paths, shown by bold lines on the fig-
Place the R1, R2, and C1 near the APL5930 as close
Connect the ground of the R2 to the GND pin by us-
Connect the one pin of the R1 to the load for Kelvin
the top-layer of PCBs. The VIN pad must have wide
size to conduct heat into the ambient air through
the VIN plane and PCB as a heat sink.
pins near the pins as close as possible for
decoupling high-frequency ripples.
placed near the load as close as possible for
decoupling high-frequency ripples.
load reduces parasitic resistance and inductance
for excellent load transient response.
and the GND pin must be connected to the ground
plane of the load.
ure 1, must have wide tracks.
as possible to avoid noise coupling.
ing a dedicated track.
sensing.
able feedback compensation.
C
CNTL
VCNTL
APL5930
GND
ANPEC Electronics Corp.
VOUT
VIN
FB
V
CNTL
C1
R2
Figure 1
C
R1
OUT
C
IN
Load
V
V
OUT
IN
12
Thermal Consideration
Refer to the figure 2, the SOP-8P is a cost-effective pack-
age featuring a small size like a standard SOP-8 and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current applica-
tions. The exposed pad must be soldered to the top-layer
VIN plane. The copper of the VIN plane on the Top layer
conducts heat into the PCB and ambient air. Please en-
large the area of the top-layer pad and the VIN plane to
reduces the case-to-ambient resistance (
Recommended Minimum Footprint
Ambient
Air
118 mil
V
plane
Top
OUT
8
1
1
2
3
4
0.050
Figure 2
SOP-8P
7
2
102 mil
0.138
Die
6
3
Unit : Inch
Exposed
Pad
7
6
5
8
PCB
0.024
5
4
www.anpec.com.tw
plane
θ
Top
V
IN
CA
).