EPCS64 Altera Corporation, EPCS64 Datasheet - Page 31

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Altera Corporation
July 2004
DATA
ASDI
nCS
DCLK
VCC
GND
Table 4–20. Serial Configuration Device Pin Description
Pin Name
2
5
1
6
3, 7, 8
4
Pin Number
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Output
Input
Input
Input
Power
Ground
Figure 4–20. Altera Serial Configuration Device 16-Pin SOIC Package Pin-Out
Diagram
Note to
(1)
Pin Type
These pins can be left floating or connected to V
convenient on the board.
Figure
DATA
Core Version a.b.c variable
N.C.
N.C.
N.C.
N.C.
nCS
V
V
CC
CC
The
configuration device to the FPGA during read/configuration
operation. During a read/configuration operations, the serial
configuration device is enabled by pulling
transitions on the falling edge of
The AS data input signal is used to transfer data serially into the
serial configuration device. It receives the data that should be
programmed into the serial configuration device. Data is latched in
the rising edge of
The active low chip select input signal toggles at the beginning and
end of a valid instruction. When this signal is high, the device is
deselected and the
enables the device and puts the device in an active mode. After
power up, the serial configuration device requires a falling edge on
the
DCLK
serial interface. The data presented on
configuration device, at the rising edge of
pin changes after the falling edge of
FPGA on the rising edge.
Power pins connect to 3.3 V.
Ground pin.
4–20:
nCS
EPCS64 Device
DATA
is provided by the FPGA. This signal provides the timing of the
EPCS16 or
1
2
3
4
5
6
7
8
(1)
(1)
(1)
(1)
signal before beginning any operation.
output signal transfers data serially out of the serial
14
13
12
11
16
15
10
(1)
(1)
(1)
(1)
9
DCLK
DATA
DCLK
ASDI
N.C.
N.C.
N.C.
N.C.
GND
V
CC
.
pin is tri-stated. When this signal is low, it
Description
Configuration Handbook, Volume 2
DCLK
DCLK
cc
.
or GND, whichever is more
ASDI
nCS
DCLK
and is latched into the
is latched to the serial
low. The
. Data on the
DATA
signal
DATA
4–31