FSA506 Newhaven Display International, Inc, FSA506 Datasheet
FSA506
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FSA506 Summary of contents
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... FSA506 AMP506 (FSA0AC197A) ...
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... FSA506 AMP506 Preliminary Specification Version 0.3 Date: 2007/06/02 Prepared by: Y.C. Lee ...
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Revise History Date Version Description 2007/03/08 V 0.1 Initialized Release 2007/04/27 V 0.2 Register setting 2007/06/02 V 0.3 General function added Owner Y.C. Y.C. Y.C. ...
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Revise History .............................................................. 3 1 Introduction .................................................................. 6 2 Block Diagram .............................................................. 7 3 System Organization.................................................... 8 3.1 MPU interface connection............................................................................................................8 3.1.1 68-series interface ........................................................................................................... 8 3.1.2 80-series interface ........................................................................................................... 8 3.2 Input Interface ..............................................................................................................................9 3.3 Memory Configuration.................................................................................................................9 3.4 ...
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Electrical Specification .............................................. 30 6.1 DC characteristics ......................................................................................................................30 6.2 AC characteristics.......................................................................................................................31 6.2.1 80-series AC timing table............................................................................................... 31 6.2.2 80-series AC timing chart .............................................................................................. 31 6.2.3 68-series AC timing table............................................................................................... 32 6.2.4 68-series AC timing chart .............................................................................................. 32 7 Package ...
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... Introduction FSA506 AMP506 is a CPU interface based TFT LCD controller. It can support panel resolution up to 640x240 pixels with 262144 colors depth. User can send either a full screen picture or a partial image by controlling the MPU with popular microprocessor interface, 18/16/9/8 bits 68-series or 80-series. ...
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Block Diagram 3.3V Regulator IM[5: Input RD Control WR CPU Data[17:0] I/F RESETB Latch POR 1.8V SRAM SRAM Control VBG FD506 VS Output HS Control DE DCLK Data[17:0] OSC LCD Panel ...
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System Organization 3.1 MPU interface connection FD506 can support both MPU interfaces with variable data bus width. User can change to different mode by configuring the input ports and related registers. These two interfaces are 68-series and 80-series 68-series: ...
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Input Interface FD506 has variable interface data input including 8/9/16/18 bits and data depth (666 or 565), therefore before writing into memory it needs to be latched and normalized. The aim of this block is to normalize the input ...
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Output unit Output controller is a unit translating the parallel data to serial one and ordering the sequence of data read from memory. It has several functions including: Control data direction of accessing memory Translate the parallel data to ...
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Output data for parallel panel out_dclk 3.5 Internal oscillator & PLL Generate 80MHz clock (SYS_CLK) to all system 3.6 POR re ...
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Pin description 3.7.1 Pin assignment ...
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Power supply Pin-no Symbol 1 R_V18 2 VCCAH 3 GNDA_REG 4 GNDA_OSC 5 GNDA_PLL 6 VCC18V_PLL 11, 18, 23, VCCK 30, 36, 43, 50, 55, 62, 70, 77, 83, 88, 95 17, 22, 29, GNDK 35, 42, 49, 61, ...
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Output pin Pin-no Symbol 59 X_VSYNC 60 X_HSYNC 64 X_ODE 65 X_OCLK 66 DO00 68 DO01 71 DO02 72 DO03 73 DO04 75 DO05 78 DO06 80 DO07 81 DO08 84 DO09 85 DO10 86 DO11 90 DO12 92 ...
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Input pin Pin-no Symbol I/O 10 X_TESTEN 12 X_TIN0 13 X_TIN1 14 X_IM0 15 X_IM1 16 X_IM2 19 X_IM3 20 X_IM4 21 X_IM5 24 X_RS 25 X_CS 26 X_WR 28 X_RD 31 X_DI00 I/O 32 X_DI01 I/O 33 X_DI02 ...
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Pin-no Symbol I/O 44 X_DI08 I/O 45 X_DI09 I/O 47 X_DI10 I/O 48 X_DI11 I/O 51 X_DI12 I/O 52 X_DI13 I/O 53 X_DI14 I/O 54 X_DI15 I/O 56 X_DI16 I/O 58 X_DI17 I/O Description Remark ...
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General Description 4.1 Input data transfer order This chip supports four bus widths, 8/9/16/18, for transporting 16 (565 (666) bits data. In some setting mode of X_IM [5:0], data has to be segmented in several parts. Once ...
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80-series mode issues a command 68-series mode issues a command 80-series mode writes a data 68-series mode writes a data ...
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Register setting command format EX: Write burst value register address from 7’h23 to 7’h26 command order command counting address value 8’h23 where WC represents writes a command and WD represents writes a ...
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80-series mode reads a command 68-series mode reads a command 80-series mode reads a data 68-series mode reads a data ...
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Read from register Following example shows how to read value in burst from register EX: read burst value from register address 7’h23 to 7’h26 command order command counting address value 8’h23 where RD represents reads a data 4.3.2 Read ...
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Register Description 5.1 Register Setting Address #00 Bit [7:0] MSB of horizontal start coordinate value Address #01 Bit [7:0] LSB of horizontal start coordinate value Address #02 Bit [7:0] MSB of horizontal end coordinate value Address #03 Bit [7:0] ...
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Address #08 Bit [7:2] [1:0] MSB of input image horizontal resolution Address #09 Bit [7:0] LSB of input image horizontal resolution Address #0A Bit [7:2] [1:0] [17:16] bits of memory write start address Address #0B Bit [7:0] [15:8] bits of ...
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Output clock selection 00: system clock divided by 2 01: system clock divided by 4 10: system clock divided by 8 11: reserved Address #11 Bit [7] Reserved [6:4] Even line of serial panel data out sequence or data ...
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Address #14 Bit [7:4] Reserved [3:0] MSB of output H sync. pulse width Address #15 Bit [7:0] LSB of output H sync. pulse width Address #16 Bit [7:4] Reserved [3:0] MSB of output DE horizontal start position Address #17 Bit ...
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Address #1C Bit [7:4] Reserved [3:0] MSB of output V sync. pulse start position Address #1D Bit [7:0] LSB of output V sync. pulse start position Address #1E Bit [7:4] Reserved [3:0] MSB of output V sync. pulse width Address ...
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Address #24 Bit [7:4] Reversed [3:0] MSB of output V total in line Address #25 Bit [7:0] LSB of output V total in line Address #26 Bit [7:2] Reserved [1:0] [17:16] bits of memory read start address Address #27 Bit ...
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Address #2d Bit [7:4] Reserved [3] Output pin X_DCON level control [2] Output clock inversion 0: Normal 1: Inverse [1:0] Image rotate 00: 0 01: 90 10: 270 11: 180 Address #30 Bit [7:4] Reserved [3:0] MSB of image horizontal ...
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Address #36 Bit [7:4] Reserved [3:0] MSB of image vertical physical resolution in memory Address #37 Bit [7:0] LSB of image vertical physical resolution in memory Address #40 Bit [7:6] Reserved [5] PLL control pins to select out frequency range ...
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Electrical Specification 6.1 DC characteristics DC Characteristics of 3.3V with 5V Tolerance I/O Cells Symbol VCCK Core power supply VCC3I Power supply VCC3O Power supply Junction temperature Tj Input low voltage Vil Input high voltage Vih Switching threshold Vt ...
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AC characteristics 6.2.1 80-series AC timing table Symbol t Enable cycle time cycle PW Enable high-level pulse width HW PW Enable low-level pulse width setup time hold time AH t Write data setup ...
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AC timing table Symbol t Enable cycle time cycle PW Enable high-level pulse width EH PW Enable low-level pulse width setup time ASE t RS hold time AHE t Write data setup time DSWE t ...
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Package Outline LQFP 100 ...