MT90820 Mitel Networks Corporation, MT90820 Datasheet - Page 7

• Manufacturer Part Number: MT90820
• Description: CMOS ST-BUS FAMILY Large Digital Switch (LDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
that a valid offset measurement is ready to be read
from the FAR register.
This feature is not available when the HMVIP
interface is enabled, i.e. when HMVIP pin is tied to
V
Memory Block Programming
The LDX device provides the capability of block
programming the connect memory block. By using
this feature, the five MSBs of the connect memory
belonging
automatically programmed with a fixed pattern
defined by the IMS register. This feature reduces the
system initialization time.
To enable the block programming mode, user have
to set the Memory Block Program (MBP) bit of the
control register to HIGH and program the IMS
register
bit = 1, and the desired pattern. The block
programming takes two frames to complete.
Delay Through the LDX
The switching of information from the input serial
streams to the output serial streams results in a
delay. Depending on the type of information to be
switched, the LDX can be programmed to perform
time-slot
throughput delay capabilities on the per-channel
basis. For voice application, variable throughput
delay can be selected ensuring minimum delay
between input and output data. In wideband data
applications, constant throughput delay can be
selected maintaining the frame integrity of the
information through the switch.
The delay through the LDX varies according to the
type of throughput delay selected in the connect
memory.
Microprocessor Port
The LDX provides an microprocessor interface with
non-multiplexed and multiplexed bus structures. The
LDX microport is compatible to Motorola multiplexed/
non-multiplexed and Intel multiplexed buses. The
multiplexed bus structure is selected by the CPU
interface Mode (IM) pin.
When the IM pin is not connected (left open) or
grounded, the LDX parallel port assumes the default
Motorola non-multiplexed bus mode. If IM pin is
DD
.
with the Block Programming Enable (BPE)
interchange
to
each
output
functions
channel
with
can
different
be
connected HIGH, the internal parallel microport
provides compatibility to MOTEL interface allowing
direct connection to Intel, National and Motorola
CPUs.
The MOTEL circuit (MOtorola and inTEL compatible
bus) automatically identifies the types of CPU Bus
connected to the LDX. This circuit uses the level of
the DS/RD input pin at the rising edge of the AS/ALE
to identify the appropriate bus timing connected to
the LDX. If DS/RD is low at the rising edge of AS/
ALE then Motorola bus timing is selected. If DS/RD
is HIGH at the rising edge of AS/ALE, then the Intel
bus timing is selected.
The LDX microport provides the access to the
internal registers, connect and data memories. All
locations can be read or written except for the data
memory which can be read only.
Internal Register and Address Memory
To access internal registers, users have to connect
the A7 pin to LOW. To access to data and connect
memories positions, users have to connect the A7
pin HIGH.
Table 2 summarizes the internal register and address
memory mapping.
Initialization of the LDX
On initialization or power up, the contents of the
connect memory can be in any states. This is a
potentially hazardous condition when multiple LDXs
outputs are tied together to form matrices, as these
output may conflict each other. The ODE pin should
be held low on power up to keep all outputs in the
high impedance condition.
CMOS
MT90820
2-185