MT9085 Mitel Networks Corporation, MT9085 Datasheet - Page 3

• Manufacturer Part Number: MT9085
• Description: CMOS PAC - Parallel Access Circuit
• Manufacturer: Mitel Networks Corporation

Pin Description
19-20 S14-S15 Serial Input/Outputs. See description for pins 2 - 9 above.
21-26 S16-S21 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial
28-33 S22-S27 Serial Input/Outputs. See description for pins 21-26 above.
36-39 S28-S31 Serial Input/Outputs. See description for pins 21-26 above.
11-16
Pin #
2-9
10
17
18
27
34
35
40
41
42
43
44
45
46
47
1
S8-S13 Serial Input/Outputs. See description for pins 2 - 9 above.
Name
S0-S7
CFPo
CKD
MCA
2/4S
V
V
V
V
V
V
V
C4i
OE
IC
IC
SS
SS
DD
SS
SS
SS
DD
Ground.
Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial
bus streams; inputs in serial to parallel mode (MCA=0), and outputs in parallel to serial mode
(MCA=1). Data rate on the serial streams can be selected to be 2.048 Mbit/s (2/4S=0) or 4.096
Mbit/s (2/4S=1). Refer to Figures 3, 4 and 5 for functional timing information.
Ground.
Supply Input. +5V.
Ground.
bus streams which are configured as inputs in serial to parallel mode (MCA =0), and outputs in
parallel to serial mode (MCA=1). Data is clocked at 2.048 Mbit/s (2/4S = 0). These input/
outputs are inactive when the device is configured for 4.096 Mbit/s operation (2/4S=1).
Ground.
Ground.
Supply Input +5V.
Clock Delay (Input). Control input which configures internal device timing.
CKD=0
CKD=1 Internal master counter is reset one C16 clock period after system frame boundary.
Timing for data input/output and for OE is affected by the level asserted on CKD. The relative
phase between the frame boundary established by F0i and output signals F0o, C2o, C4o,
DFPo, DFPo and CFPo is also affected by the state of the CKD input. See descriptions
pertaining to each specific pin for more information.
4.096MHz Clock Input. The 4.096 MHz clock signal must be phase locked to the 16.384 MHz.
clock. The falling edge of C4i is used to clock in the frame pulse (F0i).
Output Enable (Input). When low, output data bus (serial or parallel) is actively driven.
When set high, the output bus drivers are disabled. In serial to parallel mode, the outputs are
disabled immediately after OE is taken High. See Figures 6 and 21 for timing information
pertaining to parallel to serial mode.
2.048/4.096 Mbit/s Select (Input). Selects the data rate for the time division, multiplexed
serial streams. When tied low, the data rate is 2.048 Mbit/s. When tied high, the data rate is
4.096 Mbit/s.
Mode Control-A (Input). The device will perform a serial to parallel conversion when this
input is tied low. When the input is tied high, the device operates in the parallel to serial mode.
Internal Connection. Must be tied to V
Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency;
goes low 71 (CKD=0) or 68 (CKD=1) C16 clock cycles before the frame boundary established
by F0i. The signal is used by the connection memory in a typical 1k or 2k switch configuration.
See Figure 15 for timing information.
Internal Connection. Should be left unconnected.
Internal master counter is reset at the system frame boundary established by the
frame pulse (F0i).
All data input/output will be delayed by one C16 clock period.
SS
Description
for normal device operation.
CMOS
MT9085
2-127