MT90863 Mitel Networks Corporation, MT90863 Datasheet - Page 16

• Manufacturer Part Number: MT90863
• Description: 3V Rate Conversion Digital Switch
• Manufacturer: Mitel Networks Corporation

MT90863
16
15-11
8-0
Bit
10
9
Offset Value
Offset Value
FE4
ST-BUS F0i
15
HMVIP F0i
Read/Write Address:
Reset Value:
FEi Input
FEi Input
C16i
C16i
FE3
14
C4i
Name
FD8-0
FE4-0
CFE
FD9
FE2
13
Figure 8 - Example for Frame Alignment Measurement
FE1
12
0
Frame Evaluation Input Select. The binary value expressed in these bits refers
to the frame evaluation inputs, FEi0 to FEi23.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed
and bits FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to
zero, when SFE bit in the IMS register is changed from 1 to 0. This bit is read-only.
Frame Delay Bit 11. The falling edge of FE is sampled during the CLK-high
phase (FD9 = 1) or during the CLK-low phase (FD9 = 0). This bit allows the
measurement resolution to 1/2 CLK cycle. This bit is read-only.
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of the
IMS register changes from 1 to 0. (FD8 = MSB, FD0 = LSB). These bits are also
read-only
1
Table 9 - Frame Alignment (FAR) Register Bit
FE0
11
0
2
03
0000
H
1
CFE
3
10
,
H
.
2
4
FD9
9
3
5
4
6
FD8
8
(FD[8:0] = 08
(FD9 = 1, sample at CLK high phase)
5
7
(FD[8:0] = 06
(FD9 = 0, sample at CLK low phase)
FD7
6
7
8
7
9
FD6
H
Description
6
)
H
10
8
)
FD5
9
11 12
5
10
FD4
4
11 12
13
14
FD3
Advance Information
3
13
15
FD2
14
2
16
15
FD1
1
16
FD0
0