MT88L70 Zarlink Semiconductor, MT88L70 Datasheet - Page 8

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MT88L70

Manufacturer Part Number
MT88L70
Description
3 Volt Integrated DTMF Receiver
Manufacturer
Zarlink Semiconductor
Datasheet

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MT88L70
‡ Typical figures are at 25
*NOTES:
1.
2.
3.
4-30
AC Electrical Characteristics
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Used for guard-time calculation purposes only and tested at -4dBm.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
With valid tone present at input, t
are recommendations based upon network requirements.
W
M
N
G
O
U
P
U
S
P
D
N
C
O
C
K
T
T
T
L
I
I
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up (Q to StD)
Propagation delay (TOE to Q ENABLE)
Propagation delay (TOE to Q DISABLE)
Power-up time
Power-down time
Crystal/clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
°
C and are for design aid only: not guaranteed and not subject to production testing.
Characteristics
PU
equals time from PDWN going low until ESt going high.
- V
DD
=3.0V+20%/-10%, V
DC
Sym
t
t
t
t
t
t
t
t
C
LHCL
HLCL
QStD
t
t
PStD
t
t
REC
REC
t
t
PTE
PTD
t
DO
DP
DA
PQ
PU
PD
f
ID
C
LO
CL
SS
=0V, -40
3.5759 3.5795 3.5831
Min
0.5
20
20
40
5
°
C ≤ To ≤ +85
Typ
130
5.0
11
50
30
20
50
4
°
C, using Test Circuit shown in Figure 6.
Max
110
110
8.5
14
40
40
11
20
60
15
Units
MHz
ms
ms
ms
ms
ms
ms
ms
ms
pF
µs
µs
µs
ns
ns
ns
ns
%
Note 1
Note 1
Note 2
Note 2
Note 2
Note 2
TOE=V
TOE=V
TOE=V
load of 10 kΩ,
50 pF
load of 10 kΩ,
50 pF
Note 3
Ext. clock
Ext. clock
Ext. clock
Conditions
DD
DD
DD

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