MT8972B Mitel Networks Corporation, MT8972B Datasheet - Page 12

• Manufacturer Part Number: MT8972B
• Description: (MT8971B) ISO2-CMOS ST-BUS FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: Mitel Networks Corporation

MT8971B/72B
There are some major reasons for using a biphase
line code. The power density is concentrated in a
spectral region that minimizes dispersion and
differential attenuation. This can shorten the line
response and reduce the intersymbol interference
which are critical for adaptive echo cancellation.
There are regular zero crossings halfway through
every bit cell or baud which allows simple clock
extraction at the receiving end. There is no D.C.
content in the code so that phantom power feed may
be applied to the line and simple transformer
coupling may be used with no effect on the data. It is
bipolar, making data reception simple and providing
a high signal to noise ratio. The signal is then passed
through a bandpass filter which conditions the signal
for the line by limiting the spectral content from
0.2f
made available to be put onto the line biased at
V
distributed spectrum with a peak at 3/4f
transmit signal (L
L
Diagnostics Register to logic “1”. When disabled,
L
internal pull-down to allow this pin to be left not
connected in applications where this function is not
required. The receive signal is the above transmit
signal superimposed on the signal from the remote
end and any reflections or delayed symbols of the
near end signal.
9-118
OUT
OUT
Bias
Register
Baud
Status
. The resulting transmit signal will have a
DIS pin high or by writing DLO (bit 6) of the
is forced to the V
1-2
4-6
0
3
7
to 1.6f
Baud
SYNC
CHQual
OUT
Rx HK
Future
0
SYNC
Name
and on to a line driver where it is
ID
) may be disabled by holding the
Bias
Synchronization - When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
Channel Quality - These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
Housekeeping - This bit is the received housekeeping (HK) bit from the far end.
Future Functionality. These bits return Logic 1 when read.
This bit provides a hardware identifier for the DNIC revision. The MT8972B will return
a logic “0” for this bit. (Logic “1” returned for MT8972A.)
1
level. L
CHQual
OUT
2
DIS has an
Baud
Table 6. Status Register
. The
Rx HK
3
The frame format of the transmit data on the line is
shown in Figures 11 and 12 for the DN mode at 80
and 160 kbit/s. At 80 kbit/s a SYNC bit for frame
recovery, one bit of the D-channel and the B1-
channel are transmitted. At 160 kbit/s a SYNC bit,
the HK bit, two bits of the D-channel and both B1 and
B2 channels are transmitted.
If the DINB bit of the Control Register is set, the
entire D-channel is transmitted during the B1-
channel timeslot. In MOD mode the SYNC, HK and
D-channel bits are not transmitted or received but
rather a continuous data stream at 80 or 160 kbit/s is
present. No frame recovery information is present on
the line in MOD mode.
4
Future Functionality
Function
5
6
ID
7