P102-05SCL PhaseLink Corp., P102-05SCL Datasheet - Page 3

• Manufacturer Part Number: P102-05SCL
• Description: Low Skew Output Buffer
• Manufacturer: PhaseLink Corp.

3. Switching Characteristics
SWITCHING WAVEFORMS
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/22/05 Page 3
Output Frequency
Duty Cycle ( t2 ÷ t1 )
Duty Cycle ( t2 ÷ t1 )
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Jitter; Absolute Jitter
Jitter; 1-sima
Duty Cycle Timing
PARAMETERS
1.4V
t2
1.4V
t1
SYMBOL
T
T
T
T
T
dsk-dsk
T
T
cyc-cyc
Dt1
Dt2
delay
t1
skew
T
T
lock
jabs
j1-s
1.4V
r
f
Measured at 1.4V,
C
Measured at 1.4V
Measured between 0.8V
and 2.0V, C
Measured between 2.0V
and 0.8V, C
All outputs equally loaded,
C
Measured at 1.4V
Measured at V
CLKOUT pins of devices
Loaded outputs
Stable power supply, valid
clock presented on REF pin
At 10,000 cycles, C
At 10,000 cycles, C
L
L
=30pF, F
=20pF
DESCRIPTION
out
L
L
=30pF
=30pF
Output - Output Skew
= 60MHz
Output
Output
DD
/2 on the
L
L
=30pF
=30pF
1.4V
MIN.
40.0
45.0
T
25
SKEW
Low Skew Output Buffer
1.4V
TYP.
50.0
50.0
1.2
1.2
70
10
0
0
PLL102-05
MAX.
±350
60.0
55.0
250
700
150
100
1.5
1.5
1.0
60
20
UNITS
MHz
ms
ns
ns
ps
ps
ps
ps
ps
ps
%
%