TS68302MRB/C16 ATMEL Corporation, TS68302MRB/C16 Datasheet

TS68302MRB/C16

Manufacturer Part Number

TS68302MRB/C16

Description

Integrated Multiprotocol Processor IMP

Manufacturer

ATMEL Corporation

Datasheets

1.TS68302MRBC16.pdf (47 pages)

2.TS68302MRBC16.pdf (47 pages)

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Features

•

Description

The IMP is a very large-scale integration (VLSI) device incorporating the main building

blocks needed for the design of a wide variety of controllers. The device is especially

suitable to applications in the communications industry. The IMP is the first device to

offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 micro-

processor core and a flexible communications architecture. This multichannel

communications device may be configured to support a number of popular industry

interfaces, including those for the integrated services digital network (ISDN) basic rate

and terminal adapter applications. Through a combination of architectural and pro-

grammable features, concurrent operation of different protocols is easily achieved

using the IMP. Data concentrators, line cards, bridges, and gateways are examples of

suitable applications for this versatile device.

The IMP is a high-density complementary metal-oxide semiconductor (HCMOS)

device consisting of a TS68000/TS68008 microprocessor core, a system integration

block (SIB), and a communications processor (CP). The TS68302 block diagram is

shown in Figure 1.

Note:

TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family

System Integration Block Including:

Communications Processor Including:

Frequency of Operation: 16.67 MHz

Power Supply: 5 V

– Independent Direct Memory Access (IDMA) Controller

– Interrupt Controller with Two Modes of Operation

– Parallel Input/output (I/O) Ports, some with Interrupt Capability

– On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)

– Three Timers, including a Watchdog Timer

– Four Programmable Chip-select Lines with Wait-state Logic

– Programmable Address Mapping of Dual-port RAM and IMP Registers

– On-chip Clock Generator with an Output Clock Signal

– System Control:

– Main Controller (RISC Processor)

– Three Full-duplex Serial Communication Controllers (SCCs)

– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs

– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)

– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up

– Serial Management Controllers (SMCs) for IDL and GCI Channels

General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and

Nonmultiplexed Serial Interface (NMSI) Operation

to 4.096 MHz

System Control Register

Bus Arbitration Logic with Low Interrupt Latency Support

Hardware Watchdog for Monitoring Bus Activity

Low Power (Standby) Modes

Disable CPU Logic (TS68000)

Freeze Control for Debugging Selected On-chip Peripherals

DRAM Refresh Controller

GCI is sometimes referred to as IOM2.

± 10%

Integrated

Multiprotocol

Processor (IMP)

TS68302

Rev. 2117A–HIREL–11/02

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