P123-08H PhaseLink Corp., P123-08H Datasheet - Page 3

• Manufacturer Part Number: P123-08H
• Description: 3.3v Zero Delay Buffer
• Manufacturer: PhaseLink Corp.

The PLL’s feedback path must be closed by connecting FBK to one of the available eight outputs. The output driv-
ing the FBK pin will drive an (internal) output pin load of 7pF plus any additional loading placed on this output pin.
For zero-delay applications, all outputs, including the FBK pin connected to an output pin, must be loaded
equally. Varying the loading between the FBK pin and output pins can adjust the input-to-output delay.
MAXIMUM RATINGS
Supply Voltage to Ground Potential…..……………-0.5V to 4.6V
DC Input Voltage (Except REF)…….……..…-0.5V to VDD+0.5V
DC Input Voltage REF………………..……………….-0.5V to 4.6V
Storage Temperature…………………..………...…..-65 to 150 °C
Junction Temperature……………………..………………….150 °C
Static Discharge Voltage (MIL-STD-883, Method 3015)..> 2KV
OPERATING CONDITIONS
Notes: 6: Applies to both REF clock and FBK inputs.
ZERO-DELAY AND SKEW CONTROL
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 7/19/07 Page 3
Parameter
V
T
C
C
t
PU
A
DD
L
IN
Description
Supply Voltage
Commercial Operating Temperature (ambient temperature)
Industrial Operating Temperature (ambient temperature)
Load Capacitance, below 100 MHz
Load Capacitance, above 100 MHz
Input Capacitance
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
[6]
3.3V Zero Delay Buffer
(Preliminary)
Min.
0.05
3.0
-40
―
―
―
0
PL123-08
Max.
3.6
70
85
30
15
50
7
Unit
ms
°C
°C
pF
pF
pF
V