P4095 EM Microelectronic, P4095 Datasheet - Page 7

• Manufacturer Part Number: P4095
• Description: P4095 Read/write Analog Front End For 125khz Rfid Basestation
• Manufacturer: EM Microelectronic

state. Clock signal synchronous with ANT1 indicates
that PLL is in lock and that Reception chain
operation point is set. When SHD is high RDY/CLK
pin is forced low. After high to low transition on SHD
the PLL starts-up, and the reception chain is
switched on. After time T
reception
established. At this moment the same signal which is
being transmitted to ANT1 is also put to RDY/CLK
pin indicating to microprocessor that it can start
observing signal on DEMOD_OUT and giving at the
same time reference clock signal. Clock on
RDY/CLK pin is continuous, it is also present during
time the ANT drivers are OFF due to high level on
MOD pin. During the time T
transition on SHD pin RDY/CLK pin is pulled down by
100 kΩ pull down resistor. The reason for this is in
additional functionality of RDY/CLK pin in case of AM
modulation with index which is lower then 100%. In
that case it is used as auxiliary driver which
maintains lower amplitude on coil during modulation.
(see also Typical Operating Configuration)
Remark: Please refer to AN4095 for external
components calculation and limits.
Typical Operating Configuration
Read Only Mode
Read/Write mode (Low Q factor antenna)
Read/Write mode (High Q factor antenna)
C
C
C
C
DV1
DV2
DV1
DV2
L
L
A
A
C
C
+5V
+5V
+5V
+5V
RES
RES
chain
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RDY/CLK
RDY/CLK
P4095
P4095
operation
Figure 1
Figure 2
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
SET
DEMOD_OUT
DEMOD_OUT
MOD
MOD
SHD
SHD
C
C
C
C
C
C
C
C
the PLL is locked and
DC2
FCAP
DEC
DC2
FCAP
DEC
AGND
AGND
SET
point
from high to low
µP
µP
has
been
Read/Write mode (AM modulation)
Figure 1 presents P4095 used in Read Only mode.
Pin MOD is not used. It is recommended to connect
it to VSS.
Figure 2 presents typical R/W configuration for OOK
communication protocol reader to transponder (eg.
P4150). It is recommended to be used with low Q
factor antennas (up to 15).
When the antenna quality is high using configuration
of figure 1 or 2 the voltage on antenna can arrive in
the range of few hundred volts and antenna peak
current may exceed its maximum value. In such a
case the capacitive divider ratio has to be high thus
limiting the sensitivity. For such case it is better to
reduce antenna circuit quality by adding serial
resistor. In this way the antenna current is lower and
thus power dissipation of IC is reduced with
practically the same performance (Figure 3).
C
C
C
RES
C
C
DV1
DV2
DV1
DV2
L
L
A
R
A
C
R
+5V
+5V
AM
+5V
+5V
RES
SER
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RDY/CLK
RDY/CLK
P4095
P4095
© EM Microelectronic-Marin SA, 06/2000, Rev. C/296
Figure 3
Figure 4
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
DEMOD_OUT
DEMOD_OUT
MOD
MOD
SHD
SHD
C
C
C
C
C
C
C
C
FCAP
DEC
FCAP
DEC
DC2
DC2
AGND
AGND
P4095
µP
µP
7