MC100EP016A ON Semiconductor, MC100EP016A Datasheet - Page 8
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MC100EP016A
Manufacturer Part Number
MC100EP016A
Description
3.3 V ECL 8-Bit Synchronous Binary Up Counter
Manufacturer
ON Semiconductor
Datasheet
1.MC100EP016A.pdf
(12 pages)
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accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
where:
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the EP016A and the
TC output can feed the clock input of a toggle flip flop to
create a signal divided as desired with a 50% duty cycle.
CLK
To determine what value to load into the device to
Pn’s = 256 − 113 = 8F
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
PE
TC
H
H
L
Figure 4. Mod 2 to 256 Programmable Divider
PE
CE
TCLD
CLK
CLK
Q7 Q6
P7 P6
H
L
P5
Q5
L
16
Load
Figure 5. Divide by 113 EP016A Programmable Divider Waveforms
= 1000 1111
P4
Q4 Q3 Q2 Q1 Q0
L
P3
H
1001 0000
H
P2 P1 P0
Applications Information
H
H
1001 0001
COUT
COUT
TC
http://onsemi.com
MC100EP016A
DIVIDE BY 113
1111 1100
8
Table 1. Preset Values for Various Divide Ratios
2 to 256 inclusive. If divide ratios of greater than 256 are
needed multiple EP016As can be cascaded in a manner
similar to that already discussed. When EP016As are
cascaded to build larger dividers the TCLD pin will no
longer provide a means for loading on terminal count.
Because one does not want to reload the counters until all of
the devices in the chain have reached terminal count,
external gating of the TC pins must be used for multiple
EP016A divider chains.
A single EP016A can be used to divide by any ratio from
Divide
Ratio
254
255
256
112
113
114
2
3
4
5
1111 1101
de
(continued)
P7
H
H
H
H
H
H
H
L
L
L
1111 1110
P6
H
H
H
H
L
L
L
L
L
L
P5
H
H
H
H
L
L
L
L
L
L
Preset Data Inputs
1111 1111
P4
H
H
H
H
H
L
L
L
L
L
P3
H
H
H
H
H
H
L
L
L
L
P2
H
H
H
H
H
L
L
L
L
L
Load
P1
H
H
H
H
H
L
L
L
L
L
P0
H
H
H
H
L
L
L
L
L
L