MC10EP31 ON Semiconductor, MC10EP31 Datasheet
MC10EP31
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MC10EP31 Summary of contents
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... MC10EP31, MC100EP31 3. ECL D Flip−Flop with Set and Reset Description The MC10/100EP31 flip−flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip− ...
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SET Flip Flop CLK 3 R RESET 4 Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time ...
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Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out T Operating Temperature Range A T Storage Temperature ...
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Table 5. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
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Table 8. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
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Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max (Figure Propagation Delay to PLH t Output Differential PHL CLK Set/Reset Recovery RR t Setup Time S ...
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... Device Q Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10EP31D MC10EP31DG MC10EP31DR2 MC10EP31DR2G MC10EP31DT MC10EP31DTG MC10EP31DTR2 MC10EP31DTR2G MC10EP31MNR4 MC10EP31MNR4G MC100EP31D MC100EP31DG MC100EP31DR2 MC100EP31DR2G MC100EP31DT MC100EP31DTG MC100EP31DTR2 MC100EP31DTR2G MC100EP31MNR4 MC100EP31MNR4G † ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...
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K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− SEATING G PLANE PACKAGE DIMENSIONS TSSOP−8 ...
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... AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.20 0.30 2.00 BSC D D2 1.10 1.30 E 2.00 BSC E2 0.70 0.90 e 0.50 BSC K 0.20 −−− L 0.25 0.35 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10EP31/D ...