MC100H641 ON Semiconductor, MC100H641 Datasheet - Page 7

• Manufacturer Part Number: MC100H641
• Description: SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP
• Manufacturer: ON Semiconductor

Rise/Fall Skew Determination
between the T
skew for the H641 is dependent on the V
device. Notice from Figure 4 the opposite relationship of
T
the rise−to−fall skew will vary depending on V
all likelihood it will be impossible to establish the exact
value for V
be used. If this variation will be the ± 5% shown in the data
sheet the rise−to−fall skew could be established by simply
subtracting the fastest T
exercise yields 1.41 ns. If a tighter V
Figure 4 can be used to establish the rise−to−fall skew.
Specification Limit Determination Example
example. The central clock is distributed to two different
cards; on one card a single H641 is used to distribute the
clock while on the second card two H641’s are required to
supply the needed clocks. The data sheet as well as the
graphical information of this section will be used to
calculate the skew between H641a and H641b as well as the
skew between all three of the devices. Only the T
analyzed, the T
technique. The following assumptions will be used:
− All outputs will be loaded with 50 pF
− All outputs will toggle at 30 MHz
− The V
− The temperature variation between the three
− 500 lfpm air flow
the devices under these conditions. Using the power
equation yields:
thermal resistance of 41°C/W which yields a junction
temperature of 71°C with a range of 56°C to 86°C. Using the
T
propagation delay of 5.42 ns and a variation of 0.19 ns.
variation of the data sheet the 1.0 ns window provided will
be unnecessarily conservative. Using the curve of Figure 4
shows a delay variation due to a ± 3% V
± 0.075 ns. Therefore the 1.0 ns window can be reduced to
1.0 ns − (0.27 ns − 0.15 ns) = 0.88 ns. Since H641a and
H641b are on the same board we will assume that they will
PD
PD
The rise−to−fall skew is defined as simply the difference
The situation pictured in Figure 6 will be analyzed as an
devices is ± 15°C around an ambient of 45°C.
The first task is to calculate the junction temperature for
P
Using the thermal resistance graph of Figure 2 yields a
Since the design will not experience the full ± 5% V
D
versus V
= I
versus Temperature curve of Figure 3 yields a
CC
=4.3 * 48m A * 5.0 V + 5.0 V * 3.0 V * 30 MHz *
=432 mW + 203 mW = 635 mW
CC
V
50 pF * 9
CC
variation between the two boards is ± 3 %
CC
(no load) * V
CC
, the expected variation range for V
PLH
* V
PHL
between T
S
and the T
numbers can be found using the same
* f * C
PLH
CC
PLH
L
PHL
* # outputs
from the slowest T
+
and T
propagation delays. This
CC
PHL
range can be realized
CC
. Because of this
CC
applied to the
variation of
CC
PLH
CC
. Since in
PHL
http://onsemi.com
should
will be
; this
CC
7
always be at the same V
window will only be 1 ns − 0.27 ns = 0.73 ns.
between all devices of
while the skew between devices A and B will be only
around 5.42 ns, resulting in the following t
the data sheet since all outputs are equally loaded.
windows, and thus skew, obtained are significantly better
than the conservative worst case limits provided at the
beginning of this note. For very high performance designs,
this extra information and effort can mean the difference
between going ahead with prototypes or spending valuable
engineering time searching for alternative approaches.
Putting all of this information together leads to a skew
0.19 ns + 0.88 ns
(temperature + supply, and inherent device),
0.19 ns + 0.73 ns
(temperature + inherent device only).
In both cases, the propagation delays will be centered
T
T
Of course the output−to−output skew will be as shown in
This process may seem cumbersome, however the delay
PLH
PLH
=
= 4.92 ns − 5.99 ns; 1.07 ns window
(all devices)
5.00 ns − 5.92 ns; 0.92 ns window
(devices a & b)
Figure 6. Example Application
H641a
H641b
H641c
ECL
ECL
ECL
CC
; therefore the propagation delay
Q0
Q8
Q0
Q8
Q0
Q8
PLH
TTL
TTL
TTL
windows:
Card 1
Card 2