MC10EP32 ON Semiconductor, MC10EP32 Datasheet

MC10EP32

Manufacturer Part Number

MC10EP32

Description

3.3V 5V ECL / 2 Divider

Manufacturer

ON Semiconductor

Datasheet

1.MC10EP32.pdf (8 pages)

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MC10EP32

inputs and the V BB allow a differential, single–ended or AC coupled

interface to the device. If used, the V BB output should be bypassed to

ground with a 0.01 F capacitor.

Upon power–up, the internal flip–flops will attain a random state; the

reset allows for the synchronization of multiple EP32’s in a system.

December, 1999 – Rev. 1

The MC10EP32 is an integrated

The reset pin is asynchronous and is asserted on the rising edge.

Oxygen Index 28 to 34

250ps Typical Propagation Delay

3 GHz Typical Toggle Frequency

PECL mode: 3.0V to 5.5V V CC with V EE = 0V

ECL mode: 0V V CC with V EE = –3.0V to –5.5V

Internal Input Resistors: Pulldown on D, D

Q Output will default LOW with inputs open or at V EE

ESD Protection: >4KV HBM, >200V MM

V BB Output

New Differential Input Common Mode Range

Moisture Sensitivity Level 1, Indefinite Time Out of Drypack

Flammability Rating: UL–94 code V–0 @ 1/8”,

Transistor Count = 78 devices

Semiconductor Components Industries, LLC, 1999

2 Divider

Figure 1. 8–Lead Pinout (Top View) and Logic Diagram

RESET

V BB

CLK

2 divider. The differential clock

V CC

V EE

*For additional information, see Application Note

MC10EP32D

MC10EP32DR2

Z = LOW to HIGH Transition

Z = HIGH to LOW Transition

F = Divide by 2 Function

AND8002/D

CLK

CLK, CLK

Reset

V BB

Q, Q

V CC

V EE

Device

HEP32

ALYW

CLK

ORDERING INFORMATION

MARKING DIAGRAM

PIN DESCRIPTION

http://onsemi.com

TRUTH TABLE

RESET

ECL Asynchronous Reset

Reference Voltage Output

Package

CASE 751

D SUFFIX

SOIC

SO–8

Negative, 0 Supply

ECL Data Outputs

ECL Clock Inputs

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

Positive Supply

Publication Order Number:

FUNCTION

2500 Tape & Reel

98 Units/Rail

Shipping

MC10EP32/D

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