MC14093BD ON Semiconductor, MC14093BD Datasheet

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MC14093BD

Manufacturer Part Number
MC14093BD
Description
Quad 2-Input NAND Schmitt Trigger
Manufacturer
ON Semiconductor
Datasheet

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MC14093B
Quad 2-Input NAND"
Schmitt Trigger
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2–input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
2. Maximum Ratings are those values beyond which damage to the device
3. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14093B Schmitt trigger is constructed with MOS
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Triple Diode Protection on All Inputs
Pin–for–Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt–Trigger at each Input
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 2.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
1. For ordering information on the EIAJ version of
MC14093BCP
MC14093BD
MC14093BDR2
MC14093BDT
MC14093BDTEL
MC14093BDTR2
MC14093BF
MC14093BFEL
the SOIC packages, please contact your local
ON Semiconductor representative.
Device
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
http://onsemi.com
CASE 948G
CASE 751A
SOEIAJ–14
DT SUFFIX
TSSOP–14
= Assembly Location
CASE 646
CASE 965
D SUFFIX
P SUFFIX
F SUFFIX
SOIC–14
PDIP–14
SOEIAJ–14
SOEIAJ–14
TSSOP–14
TSSOP–14 2000/Tape & Reel
TSSOP–14 2500/Tape & Reel
Package
SOIC–14
SOIC–14
PDIP–14
Publication Order Number:
14
2500/Tape & Reel
14
14
1
1
1
DIAGRAMS
MC14093BCP
MARKING
See Note 1.
See Note 1.
14
MC14093B
AWLYYWW
AWLYWW
AWLYWW
1
Shipping
2000/Box
2750/Box
MC14093B/D
14093B
96/Rail
ALYW
093B
14

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MC14093BD Summary of contents

Page 1

... C 260 C Device MC14093BCP MC14093BD MC14093BDR2 MC14093BDT and V should be constrained in out MC14093BDTEL MC14093BDTR2 MC14093BF MC14093BFEL 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. 1 http://onsemi.com MARKING DIAGRAMS 14 PDIP–14 MC14093BCP P SUFFIX AWLYYWW ...

Page 2

MC14093B PIN ASSIGNMENT OUT OUT 4 11 OUT OUT ...

Page 3

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 4

SWITCHING CHARACTERISTICS (C Î Î Î Î ...

Page 5

All unused inputs connected to ground – 5.0 Vdc – 2 – – 4.0 ...

Page 6

–T– SEATING PLANE 0.13 (0.005) –A– –B– –T– SEATING 14 PL PLANE 0.25 (0.010 MC14093B ...

Page 7

K 14X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT 0.15 (0.006 –V– C 0.10 (0.004) –T– SEATING G D PLANE MC14093B PACKAGE DIMENSIONS DT SUFFIX ...

Page 8

... CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit– ...

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