MC145162 Motorola, MC145162 Datasheet - Page 7

• Manufacturer Part Number: MC145162
• Description: 60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers
• Manufacturer: Motorola

controlled by the ENB input. If the enable signal is high during
the serial data transfer, control register/reference frequency
programming is selected. If the ENB is low, programming of
the transmit and receive counters is selected. During pro-
gramming of the transmit and receive counters, both AD in
and D in pins can input the data to the transmit and receive
counters. Both counters’ data is clocked into the PLL internal
shift register at the leading edge of the CLK signal. It is not
necessary to reprogram the reference frequency counter/
control register when using the enable signal to program the
transmit/receive channels.
scheme, the most significant bit (MSB) of the programming
word identifies whether the input data is the control word or
the reference frequency data word. If the MSB is 1, the input
data is the control word (Figure 8). Also see Figure 8 and
Table 1 for control register and bit function. If the MSB is 0, the
input data is the reference frequency (Figure 9).
taining the 12–bit reference frequency data, the 14–bit auxil-
iary reference frequency counter information, the reference
frequency selection plus, the auxiliary reference frequency
counter enable bit (Figure 9).
ence frequency counter provides an additional phase refer-
ence frequency output for the loops. If AUX REF ENB bit is
low, the auxiliary reference frequency counter is forced into
MOTOROLA
The MCU programming scheme is defined in two formats
In programming the control register/reference frequency
The reference frequency data word is a 32–bit word con-
If the AUX REF ENB bit is high, the 14–bit auxiliary refer-
(OSC in
V H = High voltage level.
V L = Low voltage level.
*At this point, when both f R and f V are in phase, the output is forced to near mid supply.
NOTE: The TxPD out and RxPD out generate error pulses during out–of–lock conditions. When locked in phase and fre-
MCU PROGRAMMING SCHEME
(f in –T
quency, the output is high impedance and the voltage at that pin is determined by the low–pass filter capacitor.
REFERENCE COUNTER)
f in –R
Tx COUNTER OR
f R , REFERENCE
f V , FEEDBACK
Rx COUNTER)
RxPD out
TxPD out
Figure 7. Phase Detector/Lock Detector Output Waveforms
OR
LD
power–down mode for current saving. (Other power down
modes are also provided through the control register per
Table 2 and Figure 8.) At the falling edge of the ENB signal,
the data is stored in the registers.
nel mode: the three–pin and the four–pin interfacing
schemes. The three–pin interfacing scheme is suited for use
with the MCU SPI (serial peripheral interface) (Figure 10),
while the four–pin interfacing scheme is commonly used for
general I/O port connection (Figure 11).
select bit is set to 0. All 32 bits of data, which define both the
16–bit transmit counter and the 16–bit receive counter, latch
into the PLL internal register through the data in pins at the
leading edge of CLK. See Figures 12 and 13.
select bit is set to 1. In this scheme, the 16–bit transmit count-
er’s data enters into the AD in pin at the same time as the
16–bit receive counter’s data enters into the D in pin. This si-
multaneous entry of the transmit and receive counters
causes the programming period of the four–pin scheme to be
half that of the three–pin scheme (see Figures 14 and 15).
must be pulsed to provide falling edge to latch the shifted data
after the rising edge of the last clock. Maximum data transfer
rate is 500 kbps.
There are two interfacing schemes for the universal chan-
For the three–pin interfacing scheme, the auxiliary data
For the four–pin interfacing scheme, the auxiliary data
While programming Tx/Rx Channel Counter, the ENB pin
10 ms should be allowed for initial start–up time
for the oscillator to allow all registers to clear and
enable programming of new register values.
*
NOTE
MC145162 MC145162–1
V H
V L
V H
V L
V H
HIGH IMPEDANCE
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