MC14562B ON Semiconductor, MC14562B Datasheet

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MC14562B

Manufacturer Part Number
MC14562B
Description
128-Bit Static Shift Register
Manufacturer
ON Semiconductor
Datasheet

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MC14562B
128-Bit Static Shift
Register
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired.
1. Maximum Ratings are those values beyond which damage to the device
2. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
March, 2000 – Rev. 3
Symbol
V
The MC14562B is a 128–bit static shift register constructed with
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range
Diode Protection on All Inputs
Fully Static Operation
Cascadable to Provide Longer Shift Register Lengths
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 2.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 1.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
MC14562BCP
Device
ORDERING INFORMATION
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
http://onsemi.com
CASE 646
P SUFFIX
PDIP–14
= Assembly Location
Package
PDIP–14
Publication Order Number:
14
1
DIAGRAMS
MC14562BCP
MARKING
AWLYYWW
Shipping
MC14562B/D
25/Rail

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MC14562B Summary of contents

Page 1

... MC14562B 128-Bit Static Shift Register The MC14562B is a 128–bit static shift register constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data is clocked in and out of the shift register on the positive edge of the clock input. Data outputs are available every 16 bits, from 16 through bit 128 ...

Page 2

... Pins 4 and 11 not used. CLOCK 5 DATA MC14562B PIN ASSIGNMENT Q64 Q96 2 13 Q32 Q128 3 12 DATA CLOCK 5 10 Q16 Q112 6 9 Q48 ...

Page 3

... The formulas given are for the typical characteristics only calculate total supply current at loads other than 50 pF (50 pF – 50) Vfk where (per package pF MC14562B (Voltages Referenced – Vdc Min Max Min V 5.0 — ...

Page 4

... Data to Clock Hold Time Clock Input Rise and Fall Times 6. The formulas given are for the typical characteristics only Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MC14562B = pF, T ...

Page 5

... MC14562B V DD Q16 DATA Q32 Q48 Q64 Q80 Q96 CLOCK Q112 Q128 500 CLOCK DATA ( Figure 1. Power Dissipation Test Circuit and Waveforms http://onsemi.com ...

Page 6

... WL 50% 50% DATA IN t su(1) Q16 NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80, 96, 112, 128 in the same relationship as Q16. MC14562B TIMING DIAGRAM PULSE 32 AC TEST WAVEFORMS PULSE 16 90% 10 ...

Page 7

... –T– SEATING PLANE 0.13 (0.005) MC14562B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN B FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC14562B/D ...

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