T71L6816A Taiwan Memory Technology, T71L6816A Datasheet - Page 17

• Manufacturer Part Number: T71L6816A
• Description: Sixteen-port 10/100 Switch
• Manufacturer: Taiwan Memory Technology

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DataSheet
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U
.com
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SRAM_ADDR[15:0]
VCC
GND
VDD
SCLK
SDA
MDC
MDIO
TEST
MOD[3:0]
RST
SYSCLK
PLL_OFF
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Change to products or specifications without notice.
Symbol
CH
TE
I/O type
I/O
I/O
O
O
O
I
I
I
I
I
107, 108, 109, 110,
115, 116, 117, 118,
119, 120, 121, 122
2, 33, 65, 88, 128,
158, 167
1, 32, 64, 89, 126,
160, 165, 169, 188
90, 157, 201
107, 108, 109, 110
111, 112, 113, 114,
172
173
174
175
171
170
168
159
Pin Number
PHY Management Interfaces
Serial EEPROM Interfaces
SRAM Interfaces (Cont.)
System Interfaces
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Power Pins
Test Pins
The MDC provides the reference clock for shifting
For normal use, those p ins should be tired to low.
which is read from or written to the PHY devices.
SRAM Address Bus .
Power Pins for System .
Ground Pin .
Power Pins for Core .
Serial Clock .
Serial Data/Access .
Bi- directional serial data I/O line which is
pulled high internally.
PHY Management Interface Clock .
edges.
PHY Management Interface Data I/O.
Bi-directional serial data contains information
Test Mode Enable .
Test Mode Select .
Reset .
System Clock .
Phase-Loop-Lock enable/disable .
3.3V DC power.
DC ground.
1.8V DC power.
pulled high internally.
SCLK is used to synchronize the SDA and to be
serial data in/out from PHY device on rising
For normal use, this pin must be tire to low.
Asynchronous active low reset signal.
50MHz clock for system.
High to disable the internal PLL circuit.
P. 17
Preliminary T71L6816A
Function
Publication Date:Jun. 2001
Revision:0.A