MC74HC4040ANG ON Semiconductor, MC74HC4040ANG Datasheet
MC74HC4040ANG
Specifications of MC74HC4040ANG
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MC74HC4040ANG Summary of contents
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... Chip Complexity: 398 FETs or 99.5 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 PDIP−16 16 ...
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... Pin Reset Pin 8 = GND Figure 1. Logic Diagram ORDERING INFORMATION Device MC74HC4040AN MC74HC4040ANG MC74HC4040AD MC74HC4040ADG MC74HC4040ADR2 MC74HC4040ADR2G MC74HC4040ADTR2 MC74HC4040ADTR2G MC74HC4040AF MC74HC4040AFG MC74HC4040AFEL MC74HC4040AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb− ...
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... Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...
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... Symbol Parameter Parameter I Maximum Input Leakage Current in I Maximum Quiescent Supply CC Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS ( pF, Input t L Symbol f Maximum Clock Frequency (50% Duty Cycle) max ...
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... Maximum Input Rise and Fall Times r f (Figure 1) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). INPUTS Clock (Pin 10) Negative−edge triggering clock input. A high−to−low transition on this input advances the state of the counter. ...
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0.25 (0.010) M −A− −B− −T− SEATING PLANE 0.25 (0.010 MC74HC4040A PACKAGE DIMENSIONS ...