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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Generation Chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the V BB output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPS Data Book DL140/D). If a single-ended input is to be used, the
V BB output should be connected to the CLK input and bypassed to ground
via a 0.01 F capacitor. The V BB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
12/93
Motorola, Inc. 1996
2,
50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
75k Internal Input Pulldown Resistors
>1000V ESD Protection
The MC10/100EL34 is a low skew 2, 4, 8 clock generation chip
The common enable (EN) is synchronous so that the internal dividers
Upon startup, the internal flip-flops will attain a random state; the
4,
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
V CC
16
Q0
1
8 Clock
Q
2
EN
15
Q0
2
R
D
Q
V CC
NC
14
3
R
CLK
13
Q1
4
Q
CLK
4
Q1
12
5
3–1
R
V BB
V CC
11
6
MR
Q2
10
7
Q
V EE
8
Q2
9
8
R
REV 2
CLK
Z = Low-to-High Transition
ZZ = High-to-Low Transition
PIN
CLK
EN
MR
V BB
Q 0
Q 1
Q 2
ZZ
X
Z
MC100EL34
MC10EL34
PLASTIC SOIC PACKAGE
PIN DESCRIPTION
FUNCTION TABLE
EN
H
X
L
16
CASE 751B-05
FUNCTION
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff 2 Outputs
Diff 4 Outputs
Diff 8 Outputs
D SUFFIX
1
MR
H
L
L
FUNCTION
Divide
Hold Q 0–3
Reset Q 0–3