S12CPUV2 Motorola, S12CPUV2 Datasheet - Page 85
![no-image](/images/manufacturer_photos/0/4/459/motorola_sml.jpg)
S12CPUV2
Manufacturer Part Number
S12CPUV2
Description
MC9S12DT128 Device User Guide V02.09
Manufacturer
Motorola
Datasheet
1.S12CPUV2.pdf
(138 pages)
- Current page: 85 of 138
- Download datasheet (3Mb)
Section 6 HCS12 Core Block Description
6.1 CPU Block Description
Consult the CPU Reference Manual for information on the CPU.
6.1.1 Device-specific information
When the CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is
equivalent to 1 Bus Clock period.
6.2 HCS12 Module Mapping Control (MMC) Block Description
Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.
6.2.1 Device-specific information
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module.
6.3.1 Device-specific information
•
•
•
•
•
INITEE
– Reset state: $01
– Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special
PPAGE
– Reset state: $00
– Register is "Write anytime in all modes".
MEMSIZ0
– Reset state: $13
MEMSIZ1
– Reset state: $80
PUCR
– Reset state: $90
modes".
MC9S12DT128 Device User Guide — V02.09
85
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