25C64 CatalystSemiconductor, 25C64 Datasheet

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25C64

Manufacturer Part Number
25C64
Description
32K/64K-BitSPISerialCMOSE2PROM
Manufacturer
CatalystSemiconductor
Datasheet
DESCRIPTION
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS
E
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C32/
64 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
PIN FUNCTIONS
PIN CONFIGURATION
V SS
Advanced Information
FEATURES
CAT25C32/64
32K/64K-Bit SPI Serial CMOS E
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
V SS
CS
SO
WP
2
WP
CS
SO
SOIC Package (S)
PROM internally organized as 4Kx8/8Kx8 bits.
DIP Package (P)
1.8 to 6.0 Volt Operation
Hardware and Software Protection
Zero Standby Current
Low Power CMOS Technology
SPI Modes (0,0 &1,1)
Commercial, Industrial and Automotive
Temperature Ranges
Pin Name
10 MHz SPI Compatible
SO
SCK
WP
V
V
CS
SI
HOLD
NC
CC
SS
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
V CC
HOLD
SCK
SI
V CC
HOLD
SCK
SI
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
TSSOP Package (U14)
V
WP
CS
SO
NC
NC
NC
SS
1
2
3
4
5
6
7
Function
13
12
11
14
10
9
8
VCC
HOLD
NC
NC
SCK
NC
SI
2
PROM
TSSOP Package (U20)
V
WP
CS
NC
SO
SO
NC
NC
NC
NC
SS
1
3
4
10
2
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.
NC
NC
VCC
HOLD
HOLD
NC
SCK
SI
NC
NC
1,000,000 Program/Erase Cycles
100 Year Data Retention
Self-Timed Write Cycle
8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOPand
20-Pin TSSOP
64-Byte Page Write Buffer
Block Write Protection
– Protect 1/4, 1/2 or all of E
HOLD
SCK
WP
SO
BLOCK DIAGRAM
CS
SI
REGISTER
CONTROL
PROTECT
CONTROL
STATUS
BLOCK
LOGIC
LOGIC
WORD ADDRESS
I/O
SPI
BUFFERS
XDEC
2
PROM Array
Doc No. 25087-00 8/99 SPI-1
SHIFT REGISTERS
TIMING CONTROL
HIGH VOLTAGE/
SENSE AMPS
DECODERS
STORAGE
COLUMN
E
DATA IN
ARRAY
2
PROM

Related parts for 25C64

25C64 Summary of contents

Page 1

Advanced Information CAT25C32/64 32K/64K-Bit SPI Serial CMOS E FEATURES 10 MHz SPI Compatible 1.8 to 6.0 Volt Operation Hardware and Software Protection Zero Standby Current Low Power CMOS Technology SPI Modes (0,0 &1,1) Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION ...

Page 2

CAT25C32/64 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on any Pin with 1) Respect to V ................... –2. with Respect to V ...

Page 3

Advanced Information Figure 1. Sychronous Data Timing CSS V IH SCK VALID HI Note: Dashed Line= mode (1, 1) ...

Page 4

CAT25C32/64 FUNCTIONAL DESCRIPTION The CAT25C32/64 supports the SPI bus data transmis- sion protocol. The synchronous Serial Peripheral Inter- face (SPI) helps the CAT25C32/64 to interface directly with many of today’s popular microcontrollers. The CAT25C32/64 contains an 8-bit instruction register. (The ...

Page 5

... Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero BP1 Array Address Protected None 25C32: 0C00-0FFF 25C64:1800-1FFF 25C32: 800-0FFF 25C64:1000-1FFF 25C32: 0000-0FFF 25C64:0000-1FFF Protected WEL Blocks 0 Protected 1 Protected 0 Protected 1 Protected 0 Protected 1 Protected 5 ...

Page 6

... READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C32/64, followed by the 16-bit address(the three Most Significant Bits are don’t care for 25C64 and four most significant bits are don't care for 25C32). Figure 2. WREN Instruction Timing CS ...

Page 7

... SI line, followed by the 16-bit address (the three Most Significant Bits are don’t care for 25C64 and four most significant bits are don't care for 25C32), and then the data to be written. Pro- gramming will start after the CS is brought high. Figure 6 illustrates byte write sequence ...

Page 8

CAT25C32/64 During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) in- struction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the ...

Page 9

... Notes: (1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) CAT25C32/64 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle ...

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