SL4029B System Logic Semiconductor, SL4029B Datasheet
SL4029B
Related parts for SL4029B
SL4029B Summary of contents
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... SL4029B Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists CARRY IN,(CLOCK ENABLE), PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. ...
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... OUT CC Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V Unused outputs must be left open. System Logic SLS Semiconductor Parameter SOIC Package+ Parameter and V IN SL4029B Value Unit -0.5 to + 750 ...
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... SL4029B DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage V Maximum Low -Level IL Input Voltage V Minimum High-Level OH Output Voltage V Maximum Low-Level OL Output Voltage I Maximum Input IN Leakage Current I Maximum Quiescent CC Supply Current (per Package) I Minimum Output Low OL (Sink) Current I Minimum Output High OH (Source) Current ...
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... FUNCTION TABLE LOGIC LEVEL H BINARY COUNT L DECADE COUNT COUNTER ADVANCE AT POS. CLOCK TRANSITION L ADVANCE COUNTER AT POS. CLOCK SL4029B =t =20 ns Guaranteed Limit 25 C 125 C Unit 2 1 MHz 4 2 5.5 2.75 500 1000 ns 240 480 180 360 ...
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... SL4029B TIMING REQUIREMENTS Symbol Parameter t Minimum Pulse Width, Clock (Figure Minimum Pulse Width, Preset Enable w (Figure Minimum Setup Time, Clock to B/D or U/D su (Figure Minimum Removal Time, Preset Enable (Figure 1) rem ** t Minimum Hold Time, Clock to Carry In (Figure Minimum Setup Time, Carry In to Clock (Figure ...
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... System Logic SLS Semiconductor Figure 1. Switching Waveforms Figure 2. Switching Waveforms SL4029B ...
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... SL4029B TIMING DIAGRAM; binary mode; J1=HIGH; J2=LOW; BIN/DEC=HIGH TIMING DIAGRAM; decade mode; J1=LOW; J4=LOW; BIN/DEC=LOW System Logic SLS Semiconductor ...
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... System Logic SLS Semiconductor SL4029B EXPANDED LOGIC DIAGRAM TRUTH TABLE CLOCK ...