SL4516B System Logic Semiconductor, SL4516B Datasheet

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SL4516B

Manufacturer Part Number
SL4516B
Description
Presettable Up/Down Counter
Manufacturer
System Logic Semiconductor
Datasheet
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
synchronously clocked D -type flip-flops (with a gating structure to
provide T-type flip-flop capability) connected as counters. This
counter can be cleared by a high level on the RESET line, and can be
preset to any binary number present on the jam inputs by a high level
on the PRESET ENABLE line.
down on each positive-going clock transition. Synchronous cascading
is accomplished by connecting all clock inputs in parallel and
connecting the CARRY-OUT of a less significant stage to the CARRY-
IN of a more significant stage.
CARRY-OUT to the clock of the next stage. If the UP/DOWN input
changes during a terminal count, the CARRY-OUT must be gated with
the clock, and the UP/DOWN input must change while the clock
is high. This method provides a clean clock signal to the
subsequent counting stage.
SLS
The SL4516B Presettable Binary Up/Down Counter consists of four
If the CARRY-IN input is held low, the counter advances up or
The SL4516B can be cascaded in the ripple mode by connecting the
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 A at 18 V over full package-
temperature range; 100 nA at 18 V and 25 C
Noise margin (over full package temperature range):
System Logic
Semiconductor
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
LOGIC DIAGRAM
PIN 8= GND
PIN 16=V
CC
CL
X
X
X
X = don’t care
T
CI
H
X
X
L
L
FUNCTION TABLE
A
ORDERING INFORMATION
PIN ASSIGNMENT
= -55 to 125 C for all packages
Inputs
U/D
X
H
X
X
L
SL4516BN Plastic
SL4516BD SOIC
PE R
H
X
L
L
L
H
L
L
L
L
SL4516B
NO COUNT
COUNT UP
COUNT
PRESET
Outputs
DOWN
RESET
Mode

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SL4516B Summary of contents

Page 1

... CARRY-OUT of a less significant stage to the CARRY more significant stage. The SL4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high ...

Page 2

... SL4516B * MAXIMUM RATINGS Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin IN P Power Dissipation in Still Air, Plastic DIP Power Dissipation per Output Transistor D Tstg Storage Temperature ...

Page 3

... GND GND =0 GND =2 =4 =13 SL4516B Guaranteed Limit - 125 Unit C 3.5 3.5 3 1.5 1.5 1 4.95 4.95 4.95 V 9.95 9.95 9.95 14.95 14.95 14.95 0.05 0.05 0.05 V 0.05 0.05 0.05 0.05 0.05 0.05 ...

Page 4

... SL4516B AC ELECTRICAL CHARACTERISTICS Symbol Parameter Maximum Propagation Delay, Clock to Q (Figure PHL PLH Maximum Propagation Delay, Preset or Reset to PHL PLH Q (Figure Maximum Propagation Delay, Clock to Carry Out PHL PLH (Figure Maximum Propagation Delay, Carry In to Carry PHL ...

Page 5

... System Logic SLS Semiconductor 15 Figure 1. Switching Waveforms TIMING DIAGRAM SL4516B ...

Page 6

... SL4516B EXPANDED LOGIC DIAGRAM System Logic SLS Semiconductor ...

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