SM5838AS Nippon Precision Circuits Inc, SM5838AS Datasheet

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SM5838AS

Manufacturer Part Number
SM5838AS
Description
5120 X 8-bit Synchronous FIFO
Manufacturer
Nippon Precision Circuits Inc
Datasheet
OVERVIEW
The SM5838AS is a 5120
(first in, first out) high-speed line buffer. Internally, it
employs static CMOS circuits which mean that it
effectively has limitless data hold times. It can oper-
ate at speeds up to 33.3 MHz (normal-voltage speci-
fication).
The SM5838AS can be used to easily realize a 1-line
delay in high-speed facsimile machines and digital
copiers.
FEATURES
PACKAGE DIMENSIONS
24-pin SOP (Unit: mm)
NIPPON PRECISION CIRCUITS INC.
5120 8-bit structure
Variable-length delay (21 to 5120 bits)
33.3 MHz high-speed operation (normal-voltage
specification)
All input/outputs TTL compatible
Independent read enable and output enable pins,
allowing read address pointer increment in output
data hold and output high-impedance states
Supply voltage
• 4.5 to 5.5 V (normal-voltage specification)
• 3.0 to 4.5 V (low-voltage specification)
24-pin SOP package
Molybdenum-gate CMOS process
A3-paper 1-line (16 dots/mm) compatible
0.915
8-bit synchronous FIFO
15.8TYP
1.27 0.1
0.4
+ 0.10
- 0.05
PINOUT
5120
DOUT0
0.17
+ 0.08
- 0.07
VSS
OE
RR
RE 8
10
11
12
8-bit Synchronous FIFO
1
2
3
4
5
6
7
9
NIPPON PRECISION CIRCUITS—1
(TOP VIEW)
1.0 0.2
0 10
SM5838AS
24
23
22
21
20
19
18
17
16
15
14
13
WE
VDD
DIN5
DIN7

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SM5838AS Summary of contents

Page 1

... Internally, it employs static CMOS circuits which mean that it effectively has limitless data hold times. It can oper- ate at speeds up to 33.3 MHz (normal-voltage speci- fication). The SM5838AS can be used to easily realize a 1-line delay in high-speed facsimile machines and digital copiers. FEATURES 5120 8-bit structure Variable-length delay (21 to 5120 bits) 33 ...

Page 2

... Write enable input (write address pointer) 21 DIN3 I Write data input bit 3 22 DIN2 I Write data input bit 2 23 DIN1 I Write data input bit 1 24 DIN0 I Write data input bit 0 SM5838AS 32 32 SRAM Decoder Read address pointer Function 8 DOUT NIPPON PRECISION CIRCUITS—2 ...

Page 3

... Normal-voltage specification (CLK = 33.3 MHz); Low-voltage specification (CLK = 20 MHz Pins CLK, RR and RE. 3. Pins DIN0 to DIN7, RW, WE and OE. 4. Pins DOUT0 to DOUT7. Input/Outputs MHz Parameter Symbol Input capacitance C I Output capacitance C O SM5838AS Condition Condition min Normal-voltage specification 4.5 Low-voltage specification 3 supply Condition min typ 1 No output load – ...

Page 4

... Normal-voltage (5 V) specification 3.0V 0V 5ns CKW CLK t CKW OES OEH DIN SM5838AS 5 V supply Condition min typ 30 – 13 – 7 – 3 – 10 – 0 – 13 – 0 – 13 – 0 – 10 – 0 – – – = 3.0/2.5 V (5/3 V supply). Transition time is measured between V IH Low-voltage (3 V) specifi ...

Page 5

... CK t CKW CLK t CKW t t OEH OES DOUT t OH Load circuit 1 VDD 1.8k DOUT 1.1k SM5838AS 5 V supply Condition min typ – “Load circuit 1” “Load circuit 2” 5 Low-voltage (3 V) specification 1.8V 1.0V t OEH Hi Load circuit 2 30pF 3 V supply max min ...

Page 6

... Note the even if a reset period (t length in the write reset and read reset cycles, the reset operation does take place. SM5838AS both the CLK rising edge setup time (t time (t ). Note that a write reset cycle (read reset RH cycle) can occur simultaneously with a write cycle (read cycle) ...

Page 7

... CLK. n cycle t CKW CLK t CKW DOUT (n-1) (n) SM5838AS Data input occurs on the rising edge of CLK at the end of the write cycle. When WE goes HIGH, write operation is disabled and the write address pointer stops. n+1 cycle disable cycle WEH WES ...

Page 8

... DIN 0 1 DOUT SM5838AS n+1 cycle n+2 cycle t OEH Hi Perform reset in sync with desired delay length. 2. Stagger RW and RR timing to desired delay length. 3. Manipulate the write or read address pointer using disable incrementing to maintain sync with desired delay length. ...

Page 9

... DIN 0 1 DOUT n-word delay line timing 3 0 cycle 1 cycle CLK DIN 0 1 DOUT SM5838AS 1H n-1 n+0 2 cycle cycle cycle 2 n-2 n cycle A 1H n-1 n+0 2 cycle cycle cycle n cycle A 1H n-1 n+0 2 cycle ...

Page 10

... SM5838AS line by alternating between 2 SM5838AS devices (1 line/device). In reality, however, double the number of devices are ), then conver- SC required for luminance signal (Y) and color differ- ence signal (C) systems. And triple the number of devices are required for RGB signal systems. ...

Page 11

... CLK WE RW nH-1H DIN DOUT SM5838AS 5119 5119 nH- 5118 0 2 1819 909 909 ...

Page 12

... nH-2H DOUT 908* SM5838AS 2 pixel reduction, Also, if the same data is repeatedly read out in place of other data that has been discarded, the screen reso- n lution can be reduced without changing the data rate to realize a mosaic filter function ...

Page 13

... Wipe Function (Screen Switching) Because RE and OE operate independently, a screen wipe function can be realized using 2 SM5838AS devices by switching OE LOW/HIGH in field units. Screen wipe (OE changes in field units CLK WE RW nH-1H (A)DIN nH'-1H (B)DIN (A)RE (A)OE (A)RR nH-2H (A)DOUT 4 5 (B)RE (B)OE (B)RR nH'-2H (B)DOUT ...

Page 14

... Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. SM5838AS NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koto-ku, Tokyo 135-8430, Japan ...

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